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Innovations in the Memory System [Kõva köide]

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  • Formaat: Hardback, 151 pages, kõrgus x laius: 235x191 mm, kaal: 333 g
  • Sari: Synthesis Lectures on Computer Architecture
  • Ilmumisaeg: 10-Sep-2019
  • Kirjastus: Morgan & Claypool Publishers
  • ISBN-10: 1681736179
  • ISBN-13: 9781681736174
Teised raamatud teemal:
Innovations in the Memory SystemSuurem pilt
  • Formaat: Hardback, 151 pages, kõrgus x laius: 235x191 mm, kaal: 333 g
  • Sari: Synthesis Lectures on Computer Architecture
  • Ilmumisaeg: 10-Sep-2019
  • Kirjastus: Morgan & Claypool Publishers
  • ISBN-10: 1681736179
  • ISBN-13: 9781681736174
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781681736174.html
Märksõnad:

This is a tour through recent and prominent works regarding new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.

The memory system will soon be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits.

List of Figures
xv
List of Tables
xvii
Preface xix
Acknowledgments xxi
1 Introduction
1(2)
2 Memory System Basics for Every Architect
3(10)
2.1 DRAM vs. SRAM
3(1)
2.2 Memory Channel
4(1)
2.3 DDR Standards
5(1)
2.4 DLMMs, Ranks, Banks, Mats
5(2)
2.5 Row Buffers
7(1)
2.6 Capacity vs. Energy
8(1)
2.7 Address Mapping
9(1)
2.8 Scheduling
9(1)
2.9 DRAM Timing Parameters
10(3)
3 Commercial Memory Products
13(8)
3.1 Basic DDR3/DDR4 Channels and DIMMs
13(3)
3.2 DDR Deviations for Higher Capacity and Bandwidth
16(5)
4 Memory Scheduling
21(6)
4.1 Memory Scheduler Basics
21(1)
4.2 Early Multi-Core Memory Schedulers
22(2)
4.3 Co-Designed Schedulers
24(2)
4.4 Discussion
26(1)
5 Data Placement
27(8)
5.1 Data Interleaving
27(1)
5.2 Memory Compression
28(5)
5.2.1 IBM MXT
28(1)
5.2.2 Ekman and Stenstrom
29(1)
5.2.3 Linearly Compressed Pages (LCP)
29(1)
5.2.4 Nearly Overhead-Free Memory Compression
30(2)
5.2.5 PTMC
32(1)
5.2.6 Active Memory Expansion in the IBM Power Processors
32(1)
5.3 Discussion
33(2)
6 Memory Chip Microarchitectures
35(6)
6.1 Basics of DRAM Chip Microarchitecture
35(2)
6.2 DRAM Chip Innovations
37(3)
6.3 Discussion
40(1)
7 Memory Channels
41(10)
7.1 The Basics of Parallel and Serial Interconnects
41(4)
7.1.1 Parallel Buses
41(1)
7.1.2 Serial Buses
42(1)
7.1.3 Discussion
43(2)
7.2 Memory Interconnect Innovations
45(6)
7.2.1 Recent Work
45(4)
7.2.2 Discussion
49(2)
8 Memory Reliability
51(8)
8.1 Basics of DRAM Errors
51(3)
8.2 Memory Reliability Innovations
54(4)
8.3 Discussion
58(1)
9 Memory Refresh
59(10)
9.1 Refresh Basics
59(4)
9.2 Refresh Innovations
63(4)
9.2.1 Empirical Studies and Retention Times
63(2)
9.2.2 Alternative Hardware Techniques
65(1)
9.2.3 Alternative Software Techniques
66(1)
9.2.4 Leveraging Charge in Cells
66(1)
9.3 Discussion
67(2)
10 Near Data Processing
69(12)
10.1 NDP Implementations
70(3)
10.1.1 3D Stacked Architectures
70(1)
10.1.2 Tight Coupling on a DIMM
71(2)
10.2 In-Situ Implementations
73(4)
10.3 Programming Models and Applications
77(3)
10.3.1 Programming Approaches
77(2)
10.3.2 Broadening the Scope of NDP with Additional Workloads
79(1)
10.4 Discussion
80(1)
11 Memory Security
81(22)
11.1 Memory Timing Channels
81(6)
11.2 Oblivious RAM (ORAM)
87(4)
11.3 Memory Integrity
91(7)
11.4 Impact of Smart Memories
98(1)
11.5 Other Memory Security Issues
99(1)
11.6 Discussion
100(3)
12 Closing Thoughts
103(2)
Bibliography 105(24)
Author's Biography 129