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Integrated Power Devices and TCAD Simulation [Pehme köide]

, (Crosslight Software, Inc, Burnaby, BC, Canada), , (Crosslight Software Inc., Burnaby, Canada)
  • Formaat: Paperback / softback, 368 pages, kõrgus x laius: 254x178 mm, kaal: 680 g, 101 Tables, black and white; 330 Illustrations, black and white
  • Sari: Devices, Circuits, and Systems
  • Ilmumisaeg: 29-Mar-2017
  • Kirjastus: CRC Press
  • ISBN-10: 1138071854
  • ISBN-13: 9781138071858
Teised raamatud teemal:
Integrated Power Devices and TCAD SimulationSuurem pilt
  • Formaat: Paperback / softback, 368 pages, kõrgus x laius: 254x178 mm, kaal: 680 g, 101 Tables, black and white; 330 Illustrations, black and white
  • Sari: Devices, Circuits, and Systems
  • Ilmumisaeg: 29-Mar-2017
  • Kirjastus: CRC Press
  • ISBN-10: 1138071854
  • ISBN-13: 9781138071858
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781138071858.html

From power electronics to power integrated circuits (PICs), smart power technologies, devices, and beyond, Integrated Power Devices and TCAD Simulation provides a complete picture of the power management and semiconductor industry. An essential reference for power device engineering students and professionals, the book not only describes the physics inside integrated power semiconductor devices such lateral double-diffused metal oxide semiconductor field-effect transistors (LDMOSFETs), lateral insulated-gate bipolar transistors (LIGBTs), and super junction LDMOSFETs but also delivers a simple introduction to power management systems.

Instead of abstract theoretical treatments and daunting equations, the text uses technology computer-aided design (TCAD) simulation examples to explain the design of integrated power semiconductor devices. It also explores next generation power devices such as gallium nitride power high electron mobility transistors (GaN power HEMTs).

Including a virtual process flow for smart PIC technology as well as a hard-to-find technology development organization chart, Integrated Power Devices and TCAD Simulation gives students and junior engineers a head start in the field of power semiconductor devices while helping to fill the gap between power device engineering and power management systems.

Arvustused

"Semiconductor engineering has advanced to the point where the devicesin 3D with layout, thermal, and other effects thrown incan themselves be computer modeled, along with the processes underlying the devices. This book provides a readable engineering overview of the pre-circuit considerations." Dennis Feucht, Innovatia Laboratories, Cayo, Belize in H2Power Today, August 2014

Preface xix
About the Authors xxi
Chapter 1 Power Electronics, the Enabling Green Technology 1(26)
1.1 Introduction to Power Electronics
1(2)
1.2 History of Power Electronics
3(1)
1.3 DC/DC Converters
4(1)
1.4 Linear Voltage Regulators
4(1)
1.5 Switched Capacitor DC/DC Converters (Charge Pumps)
5(2)
1.6 Switched Mode DC/DC Converters
7(1)
1.7 Comparison between Linear Regulators, Charge Pumps, and Switched Regulators
8(1)
1.8 Topologies for Nonisolated DC/DC Switched Converters
9(8)
1.8.1 Buck Converter
9(2)
1.8.2 Boost Converter
11(2)
1.8.3 Buck-Boost Converter
13(1)
1.8.4 Cuk Converter
14(1)
1.8.5 Additional Topics in Nonisolated Converters
15(2)
1.8.5.1 Nonideal Power Elements
15(1)
1.8.5.2 Synchronous Rectification
15(1)
1.8.5.3 Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM)
16(1)
1.8.5.4 Interleaving
16(1)
1.8.5.5 Ripples
16(1)
1.8.5.6 Comparison of Nonisolated Topologies
16(1)
1.9 Topologies for Isolated Switching Converters
17(7)
1.9.1 Flyback Converters
17(1)
1.9.2 Forward Converters
18(1)
1.9.3 Full-Bridge Converters
19(2)
1.9.4 Half-Bridge Converters
21(1)
1.9.5 Push-Pull Converters
21(1)
1.9.6 Additional Topics in Isolated DC/DC Converters
22(2)
1.9.6.1 Synchronous Rectification of Isolated DC/DC Converters
22(1)
1.9.6.2 Power MOSFET Parallel Body Diode Conduction
22(1)
1.9.6.3 Transformer Utilization
23(1)
1.9.6.4 Voltage Stress on the Active Power Transistor
23(1)
1.9.7 Comparison of Isolated DC/DC Converter Topologies
24(1)
1.10 SPICE Circuit Simulation
24(1)
1.11 Power Management Systems for Battery-Powered Devices
25(1)
1.12 Summary
26(1)
Chapter 2 Power Converters and Power Management ICs 27(12)
2.1 Dynamic Voltage Scaling for VLSI Power Management
27(2)
2.2 Integrated DC/DC Converters
29(9)
2.2.1 Segmented Output Stage
31(3)
2.2.2 Transient Suppression with an Auxiliary Stage
34(4)
2.3 Summary
38(1)
Chapter 3 Semiconductor Industry and More than Moore 39(12)
3.1 Semiconductor Industry
39(1)
3.2 History of the Semiconductor Industry
39(3)
3.2.1 A Brief Timeline
39(1)
3.2.2 The Traitorous Eight
39(1)
3.2.3 Historical Road Map of the Semiconductor Industry
39(3)
3.3 Food Chain Pyramid of the Semiconductor Industry
42(4)
3.3.1 Level 1: Wafer and EDA Tools
42(1)
3.3.2 Level 2: Device Engineering
43(1)
3.3.3 Level 3: IC Design
44(1)
3.3.4 Level 4: Manufacturing, Packaging, and Testing
44(1)
3.3.5 Level 5: Systems and Software
45(1)
3.3.6 Level 6: Marketing and Sales
45(1)
3.4 Semiconductor Companies
46(1)
3.5 More than Moore
47(4)
Chapter 4 Smart Power IC Technology 51(16)
4.1 Smart Power IC Technology Basics
51(1)
4.2 Smart Power IC Technology: Historical Perspective
51(3)
4.3 Smart Power IC Technology: Industrial Perspective
54(8)
4.3.1 Engineering Groups of a Smart Power IC Technology
54(2)
4.3.1.1 Process Integration
54(1)
4.3.1.2 TCAD Support
55(1)
4.3.1.3 Compact Modeling
55(1)
4.3.1.4 Device Design
55(1)
4.3.1.5 ESD Design
55(1)
4.3.1.6 Process Design Kit
56(1)
4.3.1.7 IC Design Group
56(1)
4.3.1.8 Reliability Group
56(1)
4.3.1.9 Packaging
56(1)
4.3.2 Smart Power IC Technology Development Flow
56(1)
4.3.3 Planning Stage
56(1)
4.3.4 Process Integration and Device Design
57(3)
4.3.5 Layout, Tape-Out, Fabrication, and Test
60(1)
4.3.6 Reliability and Qualification
60(1)
4.3.7 Survey of Current Smart Power Technology
61(1)
4.4 Smart Power IC Technology: Technological Perspective
62(5)
4.4.1 Devices for Smart Power Technology
62(1)
4.4.2 Design Considerations for Smart Power IC Technology
63(3)
4.4.2.1 Power MOSFETs
63(1)
4.4.2.2 LIGBTs
64(1)
4.4.2.3 Analog Active Devices
64(1)
4.4.2.4 Resistors
65(1)
4.4.2.5 Capacitors
65(1)
4.4.2.6 Voltage and Frequency Trims
65(1)
4.4.2.7 Logic/Digital NMOS and PMOS
65(1)
4.4.2.8 System-Level Design and Fabrication Considerations
65(1)
4.4.3 Isolation Methods
66(1)
Chapter 5 Introduction to TCAD Process Simulation 67(20)
5.1 Overview
67(1)
5.2 Mesh Setup and Initialization
67(2)
5.3 Ion Implantation
69(3)
5.3.1 Analytical Models
69(1)
5.3.2 Multiple-Layer Implantation
70(1)
5.3.3 Monte Carlo Simulation
70(2)
5.4 Deposition
72(1)
5.5 Oxidation
72(3)
5.5.1 Dry Oxidation
73(1)
5.5.2 Wet Oxidation
73(1)
5.5.3 Oxidation Models
73(4)
5.5.3.1 Moving Boundaries
73(1)
5.5.3.2 2D Analytical Models
74(1)
5.5.3.3 Numerical Models
74(1)
5.5.3.4 LOCOS Growth Example
75(1)
5.6 Etching
75(2)
5.7 Diffusion
77(3)
5.7.1 Diffusion Mechanisms
77(1)
5.7.1.1 Direct Diffusion Mechanism
77(1)
5.7.1.2 Vacancy Mechanism
77(1)
5.7.1.3 Interstitials Mechanism
77(1)
5.7.2 Diffusion Models
78(9)
5.7.2.1 Fermi Diffusion Model
78(1)
5.7.2.2 Two-Dimensional Diffusion Model
78(1)
5.7.2.3 Fully Coupled Diffusion Model
78(1)
5.7.2.4 Steady-State Diffusion Model
79(1)
5.7.2.5 Oxide Enhanced (Retarded) Diffusion
79(1)
5.8 Segregation
80(2)
5.9 Process Simulator Models Calibration
82(1)
5.10 Introduction to 3D TCAD Process Simulation
82(2)
5.11 GPU Simulation
84(3)
Chapter 6 Introduction to TCAD Device Simulation 87(34)
6.1 Overview
87(1)
6.2 Basics about Device Simulation
87(6)
6.2.1 Drift-Diffusion Model
87(1)
6.2.2 Discretization
87(1)
6.2.3 Newton's Method
88(1)
6.2.4 Initial Guess and Adaptive Bias Stepping
89(1)
6.2.5 Convergence Issues
90(1)
6.2.6 Boundary Conditions
91(1)
6.2.6.1 Ohmic Contact
91(1)
6.2.6.2 Schottky Contacts
91(1)
6.2.6.3 Neumann Boundaries
92(1)
6.2.6.4 Lumped Elements
92(1)
6.2.7 Transient Simulation
92(1)
6.2.8 Mesh Issues
93(1)
6.3 Physical Models
93(15)
6.3.1 Carrier Statistics
93(1)
6.3.2 Incomplete Ionization of Impurities
93(1)
6.3.3 Heavy Doping Effect
94(1)
6.3.4 SRH and Auger Recombination
94(1)
6.3.5 Avalanche Breakdown and Impact Ionization
94(6)
6.3.5.1 Avalanche Breakdown
94(1)
6.3.5.2 Impact Ionization Coefficients
95(1)
6.3.5.3 Chynoweth's Law
95(1)
6.3.5.4 Baraff Model
96(1)
6.3.5.5 Fulop's Approximation
96(1)
6.3.5.6 Okuto-Crowell Model
96(1)
6.3.5.7 Lackner Model
96(1)
6.3.5.8 Mean Free Path Model
97(1)
6.3.5.9 Multiplication Factor and Ionization Integral
98(1)
6.3.5.10 Critical Electric Field
99(1)
6.3.5.11 Analytical Breakdown Voltage
100(1)
6.3.5.12 Benchmark Comparison of Avalanche Breakdown Models
100(1)
6.3.6 Carrier Mobility
100(6)
6.3.6.1 Models Overview
101(1)
6.3.6.2 Constant Mobility
101(1)
6.3.6.3 Two-Piece Mobility Model
102(1)
6.3.6.4 Canali or Beta Model
102(1)
6.3.6.5 Transferred Electron Model
102(1)
6.3.6.6 Poole-Frenkel Field Enhanced Mobility Model
102(1)
6.3.6.7 Impurity Dependence of the Low Field Mobility Model
103(1)
6.3.6.8 Intel's Local Field Models
103(1)
6.3.6.9 Lombardi Model
103(1)
6.3.6.10 Comparison of Different Diffusion Models
104(1)
6.3.6.11 GaN Mobility Model (MTE Model)
104(2)
6.3.7 Thermal and Self-Heating
106(1)
6.3.7.1 Heat Flow and Temperature Distribution
106(1)
6.3.8 Bandgap Narrowing Effect
107(1)
6.4 AC Analysis
108(4)
6.4.1 Introduction
108(1)
6.4.2 Basic Formulas
108(3)
6.4.3 AC Analysis in TCAD
111(1)
6.5 Trap Model in TCAD Simulation
112(3)
6.5.1 Trap-Charge States
112(1)
6.5.2 Trap Dynamics
112(3)
6.6 Quantum Tunneling
115(4)
6.6.1 Importance of Quantum Tunneling for Power Devices
115(1)
6.6.2 Basic Theory of Tunneling for TCAD Simulation
116(3)
6.6.3 Introduction to Nonequilibrium Green's Function for Tunneling
119(1)
6.7 Device Simulator Models Calibration
119(2)
Chapter 7 Power IC Process Flow with TCAD Simulation 121(32)
7.1 Overview
121(1)
7.2 A Mock-Up Power IC Process Flow
121(2)
7.2.1 Process Flow Steps
121(1)
7.2.2 Structure View of the Mock-Up Process Flow
121(2)
7.3 Smart Power IC Process Flow Simulation
123(30)
7.3.1 P+ Substrate
123(1)
7.3.2 N+ Buried Layer
123(1)
7.3.3 Epitaxial Layer Growth and Deep N Link
124(3)
7.3.4 High-Voltage Twin-Well
127(1)
7.3.5 P-Body Implant for n-LDMOS
128(2)
7.3.6 Active Area/Shallow Trench Isolation (STI)
130(4)
7.3.7 N-Well and P-Well
134(2)
7.3.8 Low-Voltage Twin Wells
136(1)
7.3.9 Thick Gate and Thin Gate Oxide
137(3)
7.3.10 Poly Gate
140(2)
7.3.11 NLDD and PLDD
142(1)
7.3.12 Sidewall Spacer
143(1)
7.3.13 NSD and PSD
144(2)
7.3.14 Back-End of the Line
146(7)
Chapter 8 Integrated Power Semiconductor Devices with TCAD Simulation 153(86)
8.1 PN Junction Diodes
153(24)
8.1.1 PN Junction Basics
153(1)
8.1.2 Lateral PN Junction Diode at Equilibrium
154(3)
8.1.3 Forward Conduction (On-State)
157(2)
8.1.4 Reverse Bias of a PN Junction Diode
159(1)
8.1.5 Lateral PN Junction Diode with NBL
160(1)
8.1.6 Breakdown Voltage Enhancement of the PN Junction Diode
160(8)
8.1.6.1 Basic Understanding of How to Improve Breakdown Voltage
161(2)
8.1.6.2 Different P-Substrate Doping for the PN Junction Diode without NBL
163(2)
8.1.6.3 Breakdown Enhancement for Diode with NBL
165(3)
8.1.6.4 Reverse Leakage Current Path with Substrate Contact
168(1)
8.1.7 Reverse Recovery
168(2)
8.1.7.1 Basic Understanding of Diode Reverse Recovery
168(2)
8.1.7.2 Diode Reverse Recovery TCAD Simulation
170(1)
8.1.7.3 TCAD Simulations for Carrier Lifetime Engineering
170(1)
8.1.8 Schottky Diode
170(4)
8.1.9 Zener Diode
174(1)
8.1.10 Small Signal Model for PN Junction Diode
175(2)
8.2 Bipolar Junction Transistors
177(16)
8.2.1 Basic Operation of NPN BJTs
178(3)
8.2.1.1 Simulation Structure
178(2)
8.2.1.2 Collector and Base Current
180(1)
8.2.1.3 Transistor Gain and Gummel Plot
180(1)
8.2.2 NPN BJT Breakdown
181(4)
8.2.2.1 BVCBO
181(1)
8.2.2.2 BVEBO
181(1)
8.2.2.3 BVCEO
181(2)
8.2.2.4 BVCES
183(1)
8.2.2.5 Comparison of the Four Types of NPN Breakdown
184(1)
8.2.3 BJT I-V Family of Curves
185(1)
8.2.4 Kirk Effect
186(1)
8.2.5 BJT Thermal Runaway and Second Breakdown Simulation
187(5)
8.2.6 BJT Small Signal Model and Cutoff Frequency Simulation
192(1)
8.2.6.1 Cutoff Frequency
193(1)
8.3 LDMOS
193(46)
8.3.1 Breakdown Voltage Improvement
194(27)
8.3.1.1 Basic LDMOS Structure with N-Type Epitaxial Layer (LDMOS I)
194(2)
8.3.1.2 LDMOS with Shielding Plate (LDMOS II)
196(5)
8.3.1.3 LDMOS with STI in the Drain-Drift Region (LDMOS III)
201(2)
8.3.1.4 LDMOS with Both STI Oxide and Field Plate (LDMOS IV)
203(3)
8.3.1.5 LDMOS with RESURF from P-epi Layer (LDMOS V)
206(3)
8.3.1.6 LDMOS with P-epi RESURF and STI (LDMOS VI)
209(3)
8.3.1.7 LDMOS with Double RESURF (LDMOS VII)
212(6)
8.3.1.8 LDMOS Multiple RESURF (LDMOS VIII)
218(3)
8.3.1.9 Comparison of 3D Surface Plot of Electric Field
221(1)
8.3.2 Parasitic NPN BJTs in LDMOS
221(2)
8.3.3 LDMOS On-State Resistance
223(4)
8.3.3.1 Specific On-Resistance
225(1)
8.3.3.2 On-Resistance Contribution
225(1)
8.3.3.3 Comparison of Breakdown Voltage and On-Resistance
226(1)
8.3.4 LDMOS Threshold Voltage
227(1)
8.3.5 LDMOS with Radiation Hardening Design
228(1)
8.3.6 LDMOS I-V Family of Curves
229(1)
8.3.7 LDMOS Self-Heating
230(2)
8.3.8 LDMOS Parasitic Capacitances
232(2)
8.3.9 LDMOS Gate Charge
234(2)
8.3.10 LDMOS Unclamped Inductive Switching (UIS)
236(1)
8.3.11 Compact Models of LDMOS
237(2)
Chapter 9 Integrated Power Semiconductor Devices with 3D TCAD Simulations 239(42)
9.1 3D Device Layout Effect
239(3)
9.2 3D Simulation of LIGBT
242(12)
9.2.1 About LIGBT
242(1)
9.2.2 Segmented Anode LIGBT
243(2)
9.2.3 3D Process Simulation of Segmented Anode LIGBT
245(3)
9.2.4 3D Device Simulation of Segmented Anode LIGBT
248(6)
9.2.4.1 Forward Characteristic Simulation
248(3)
9.2.4.2 LIGBT Turnoff Transient Simulation
251(2)
9.2.4.3 Forward I-V Family of Curves Comparison with LDMOS
253(1)
9.3 Super Junction LDMOS
254(14)
9.3.1 Basic Concept
254(7)
9.3.1.1 How to Choose the Pillar Width WN
255(3)
9.3.1.2 About Dose Balance
258(2)
9.3.1.3 On-Resistance
260(1)
9.3.2 Super Junction LDMOS Structure
261(2)
9.3.3 3D Process Simulation of Super Junction LDMOS
263(1)
9.3.4 3D Device Simulation of Super Junction LDMOS
264(1)
9.3.5 3D Simulation of a Standard LDMOS with the Same N-Drift Doping
264(2)
9.3.6 3D Simulation of a Standard LDMOS with Reduced N -DriftDoping
266(1)
9.3.7 Comparison of Super Junction LDMOS and Standard LDMOS
267(1)
9.4 Super Junction Power FinFET
268(6)
9.4.1 Process Flow of the Super Junction Power FinFET
269(1)
9.4.2 Measurement Results of Super Junction Power FinFET
270(1)
9.4.3 3D Simulation of Super Junction Power FinFET
271(3)
9.5 Large Interconnect Simulation
274(7)
9.5.1 3D Process Simulation of the Large Interconnect
275(5)
9.5.1.1 Substrate
276(1)
9.5.1.2 Contacts
276(1)
9.5.1.3 Metall
277(1)
9.5.1.4 Vial
277(1)
9.5.1.5 Metal2
277(2)
9.5.1.6 Via2
279(1)
9.5.1.7 Metal3
279(1)
9.5.2 3D Device Simulation of the Large Interconnect
280(1)
Chapter 10 GaN Devices, an Introduction 281(26)
10.1 Compound Materials versus Silicon
281(1)
10.2 Substrate Materials for GaN Devices
282(1)
10.3 Polarization Properties of III-Nitride Wurtzite
283(4)
10.3.1 Microscopic Dipoles and Polarization Vector
283(1)
10.3.2 Crystal Structure and Polarization
284(1)
10.3.3 Ideal c0/a0 Ratio for Zero Net Polarization
284(3)
10.3.3.1 Strain-Induced Polarization
285(1)
10.3.3.2 Empirical Approach to Modeling Polarization
286(1)
10.4 AlGaN/GaN Heterojunction
287(5)
10.4.1 Band Diagram Plots with a Fixed Al Mole Fraction
288(1)
10.4.2 Band Diagram Plots with a Fixed AlGaN Thickness
289(1)
10.4.3 AlGaN/GaN Structure with Doped AlGaN or GaN Layer
289(2)
10.4.4 AlGaN/GaN Structure with Metal Contacts
291(1)
10.5 Traps in AlGaN/GaN Structure
292(2)
10.6 A Simple AlGaN/GaN HEMT
294(3)
10.6.1 Device Structure
294(1)
10.6.2 Id-Vg Curves for GaN HEMT
294(1)
10.6.3 Summary
295(2)
10.7 GaN Power HEMT Example I
297(3)
10.7.1 Device Structure
297(1)
10.7.2 Impact Ionization Coefficient of GaN Material
297(2)
10.7.3 Breakdown Simulation of GaN HEMT
299(1)
10.8 GaN Power HEMT Example II
300(1)
10.9 Gate Leakage Simulation of GaN HEMT
301(4)
10.9.1 Device Structure
301(1)
10.9.2 Models and Simulation Setup
301(1)
10.9.3 Gate Leakage Simulation
302(3)
10.9.3.1 Pure TCAD Simulation
302(2)
10.9.3.2 TCAD Simulation with Slow Transient
304(1)
10.9.3.3 TCAD Simulation with Equivalent Circuits
304(1)
10.10 Market Prospect of Compound Semiconductors for Power Applications
305(2)
Appendix A: Carrier Statistics 307(2)
Appendix B: Process Simulation Source Code 309(12)
Appendix C: Trap Dynamics and AC Analysis 321(2)
Bibliography 323(8)
Index 331
Yue Fu obtained his Ph.D from the University of Central Florida, Orlando, USA and his BS from Zhejiang University, China. He is currently the vice president of Crosslight Software, Inc., Vancouver, British Columbia, Canada. Dr. Fu is a senior member of IEEE and has more than ten years of industry and academic experience in power semiconductor devices and power electronics. He holds multiple US patents and has authored or co-authored numerous peer-reviewed papers.

Zhanming (Simon) Li obtained his Ph.D from the University of British Columbia, Vancouver, Canada in 1988. He was with the National Research Council of Canada (NRCC) from 1988 to 1995, where he developed semiconductor device simulation software. In 1995, he founded Crosslight Software, Inc., Vancouver, British Columbia, Canada with simulation technology transferred from the NRCC. Since then, Dr. Li has been the chief designer of many semiconductor process and device simulation software packages. He has been actively involved in research of TCAD simulation technology and authored or coauthored over 70 research papers.

Wai Tung Ng received his BAS, MAS, and Ph.D in electrical engineering from the University of Toronto, Ontario, Canada in 1983, 1985, and 1990, respectively. He was a member of technical staff at Texas Instruments, Dallas, USA from 1990 to 1991. He started his academic career at the University of Hong Kong in 1992. Dr. Ng returned to the University of Toronto as a faculty member in 1993 and is currently a full professor. His research is focused on the areas of power management integrated circuits, integrated DC-DC converters, smart power integrated circuits, power semiconductor devices, and fabrication processes.

Johnny Kin-On Sin obtained his BAS, MAS, and Ph.D in electrical engineering from the University of Toronto, Ontario, Canada in 1981, 1983, and 1988, respectively. He was a senior member of the research staff of Philips Research North America, Briarcliff Manor, New York, USA from 1988 to 1991. He joined the Department of Electronic and Computer Engineering at the Hong Kong University of Science and Technology in 1991 and is currently a full professor. An IEEE fellow, Dr. Sin is the holder of 13 patents and author of over 280 technical papers. His research interests include novel power semiconductor devices and power system-on-chip technologies.