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1 | (16) |
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Microsystems for the Automotive Industry |
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3 | (6) |
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III-V Nitride-based LEDs and Lasers: Current Status and Future Opportunities |
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9 | (3) |
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Prospects for Quantum Computing |
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12 | (5) |
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Session 2: Process Technology-Gate Dielectrics-Zr and Hf Oxides |
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17 | (26) |
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Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Depostion |
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19 | (4) |
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Si-Doped Aluminates for High Temperature Metal-Gate CMOS: Zr-Al-Si-O, A Novel Gate Dielectric for Low Power Applications |
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23 | (4) |
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MOS Characteristics of Ultra Thin Rapid Thermal CVD ZrO2 and Zr Silicate Gate Dielectrics |
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27 | (4) |
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High Quality Untra Thin CVD HfO2 Gate Stack with Poly-Si Gate Electrode |
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31 | (4) |
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MOSFET Devices with Polysilicon on Single-Layer HfO2 High-K Dielectrics |
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35 | (4) |
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Characteristics of TaN Gate MOSFET with Ultrathin Hafnium Oxide (8A-12A) |
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39 | (4) |
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Session 3: CMOS Devices-Sub-50nm Devices |
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43 | (26) |
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30nm Physical Gate Length CMOS Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays |
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45 | (4) |
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45-nm Gate Length CMOS Technology and Beyond using Steep Halo |
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49 | (4) |
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SALVO Process for Sub-50 nm Low-VT Replacement Gate CMOS with KrF Lithography |
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53 | (4) |
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Complementary Silicide Source/Drain Thin-Body MOSFETs for the 20nm Gate Length Regime |
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57 | (4) |
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50-nm Vertical Sidewall Transistors with High Channel Doping Concentrations |
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61 | (4) |
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50-nm Vertical Replacement-Gate (VRG) pMOSFETs |
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65 | (4) |
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Session 4: Solid State Devices-Power Device Technology |
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69 | (22) |
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Vertical Power-MOSFETs with Local Channel Doping |
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71 | (4) |
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SOA Improvement by a Double RESURF LDMOS Technique in a Power IC Technology |
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75 | (4) |
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Temperature Dependence of Avalanche Multiplication in Spiked Electric Fields |
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79 | (4) |
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Electrical-Thermal Coupling Mechanism on Operating Limit of LDMOS Transistor |
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83 | (4) |
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Reduction of Metal-Semiconductor Contact Resistance by Embedded Nanocrystals |
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87 | (4) |
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Session 5: Modeling and Simulation-Hot Carrier and Transport Modeling |
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91 | (26) |
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Simulation of Si-SiO2 Defect Generation in CMOS Chips: from Atomistic Structure to Chip Failure Rates (Invited) |
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93 | (4) |
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Impact Ionization and Photon Emission in MOS Capacitors and FETs |
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97 | (4) |
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An Accurate, Experimentally Verified Electron Minority Carrier Mobility Model for Si and SiGe |
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101 | (4) |
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Enhanced Secondary Electron Injection in Novel SiGe Flash Memory Devices |
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105 | (4) |
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Efficiency and Stochastic Error of Monte Carlo Device Simulations |
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109 | (4) |
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Ensemble Monte Carlo/Molecular Dynamics Simulation of Gate Remote Charge Effects in Small Geometry MOSFETs |
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113 | (4) |
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Session 6: CMOS and Interconnect Reliability-Reliability of Advanced Technologies |
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117 | (26) |
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Optimizing the Electromigration Performance of Copper Interconnects (Invited) |
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119 | (4) |
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Improvement of Thermal Stability of Via Resistance in Dual Damascene Copper Interconnection |
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123 | (4) |
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ESD Protection Scheme Using CMOS Compatible Vertical Bipolar Transistor For 130nm CMOS Generation |
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127 | (4) |
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Reliability Issues for Silicon-on-Insulator (Invited) |
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131 | (4) |
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Hot Carrier Reliability for 0.13μm CMOS Technology with Dual Gate Oxide Thickness |
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135 | (4) |
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Valence-Band Tunneling Enhanced Hot Carrier Degradation in Ultra-Thin Oxide nMOSFETs |
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139 | (4) |
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Session 7: Integrated Circuits and Manufacturing-Analog/RF and 3D ICs |
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143 | (30) |
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COM2 SiGe Modular BiCMOS Technology for Digital, Mixed-Signal, and RF Applications |
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145 | (4) |
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A 73GHz fT 0.18μm RF-SiGe BiCMOS Technology Considering Thermal Budget Trade-off and with Reduced Boron-Spike Effect on HBT Characteristics |
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149 | (4) |
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Integration of Thin Film MIM Capacitors and Resistors into Copper Metalization Based RF-CMOS and Bi-CMOS Technologies |
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153 | (4) |
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A High Reliability Metal Insulator Metal Capacitor for 0.18 μm Copper Technology |
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157 | (4) |
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Three Dimensional CMOS Integrated Circuits on Large Grain Polysilicon Films |
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161 | (4) |
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Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology |
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165 | (4) |
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Novel Silicon Epitaxy for Advanced MOSFET Devices (Invited) |
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169 | (4) |
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Session 8: Quantum Electronics and Compound Semiconductors-High Speed Compound Semiconductor Devices |
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173 | (22) |
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InP HEMT Amplifier Development for G-band (140-220 GHz) Applications (Invited) |
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175 | (3) |
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Abrupt Junction InP/GaAsSb/InP Double Hetero-junction Bipolar Transistors with FT as High as 250 GHz and BVCEO>6V |
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178 | (4) |
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Metamorphic HFETs on GaAs with InP-Subchannels for Device Performance Improvements |
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182 | (4) |
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Simulation of InAIAs/InGaAs High Electron Mobility Transistors with a Single Set of Physical Parameters |
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186 | (4) |
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Reliability Study of Parasitic Source and Drain Resistances of InP-Based HEMTs |
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190 | (5) |
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Session 9: Detectors, Sensors and Displays-Si Thin Film Transistors |
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195 | (26) |
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Low Temperature Poly-Si TFT-Electrophoretic Displays (TFT-EPDs) with Four Level Gray Scale |
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197 | (4) |
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High Density, Low Parasitic Direct Integration by Fluidic Self Assembly (FSA) (Invited) |
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201 | (4) |
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A New Dopant Activation Technique for Poly-Si TFTs with a Self-Aligned Gate-Overlapped LDD Structure |
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205 | (4) |
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Selective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Laser Irradiation |
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209 | (4) |
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A New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealing |
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213 | (4) |
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Reliability of Low Temperature Poly-Si TFT Employing Counter-Doped Lateral Body Terminal |
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217 | (4) |
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Session 10: CMOS Devices-Device Scaling |
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221 | (31) |
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80 nm Poly-Silicon Gated n-FETs with Ultra-Thin Al2O3 Gate Dielectric for ULSI Applications |
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223 | (4) |
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Extending Gate Dielectric Scaling Limit by NO Oxynitride: Design and Process Issues for Sub-100 nm Technology |
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227 | (4) |
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Controlling Floating-Body Effects for 0.13μm and 0.10μm SOI CMOS |
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231 | (4) |
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CMOS Device Scaling Beyond 100nm (Invited) |
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235 | (4) |
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80nm CMOSFET Technology Using Double Offset-Implanted Source/Drain Extension and Low Temperature SiN Process |
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239 | (4) |
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Source/Drain Engineering for Sub-100 nm CMOS Using Selective Epitaxial Growth Technique |
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243 | (4) |
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Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design |
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247 | (5) |
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Session 11: Process Technology-Advanced Interconnect Technology |
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252 | (17) |
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Current and Future Low-k Dielectrics for Cu Interconnects (Invited) |
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253 | (4) |
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Process Design Methodology for Via-Shape-Controlled, Copper Dual-Damascene Interconnects in Low-k Organic Film |
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257 | (4) |
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Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects |
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261 | (4) |
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A High Reliability Copper Dual-Damascene Inter-connection with Direct-Contact Via Structure |
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265 | (4) |
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Session 12: Modeling and Simulation-Quantum and Atomic Scale Effects in MOSFETs |
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269 | (26) |
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Vth Fluctuation Induced by Statistical Variation of Pocket Dopant Profile |
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271 | (4) |
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Role of Long-Range and Short-Range Coulomb Potentials in Threshold Characteristics under Discrete Dopants in Sub-0.1 μm Si-MOSFETs |
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275 | (4) |
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Random Telegraph Signal Amplitudes in Sub 100 nm (Decanano) MOSFETs: A 3D `Atomistic' Simulation Study |
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279 | (4) |
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A Full-Band Monte Carlo Model for Silicon Nanoscale Devices with a Quantum Mechanical Correction of the Potential |
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283 | (4) |
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Quantum Effects in MOSFETs: Use of an Effective Potential in 3D Monte Carlo Simulation of Ultra-Short Channel Devices |
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287 | (4) |
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Quantum Effects Along the Channel of Ultra-Scaled Si-Based MOSFETs? |
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291 | (4) |
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Session 13: Solid State Devices-Nanoelectronics |
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295 | (26) |
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Single-Electron Pass-Transistor Logic: Operation of its Elemental Circuit |
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297 | (4) |
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A Single-Electron Shut-Off Transistor for Scalable Sub-0.1-μm Memory |
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301 | (4) |
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Engineering Variations: Towards Practical Single-Electron (Few-Electron) Memory |
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305 | (4) |
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Characteristics of P-Channel Si Nano-Crystal Memory |
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309 | (4) |
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Non-Volatile Si Quantum Memory with Self-Aligned Doubly-Stacked Dots |
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313 | (4) |
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A Novel FET-Type Ferroelectric Memory with Excellent Data Retention Characteristics |
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317 | (4) |
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Session 14: CMOS and Interconnect Reliability-Reliability of Thin Oxides |
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321 | (26) |
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Substrate Enhanced Degradation of CMOS Devices |
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323 | (4) |
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Degradation of Ultra-Thin Gate Oxides Accompanied by Hole Direct Tunneling: Can We Keep Long-Term Reliability of p-MOSFETs? |
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327 | (4) |
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Experimental and Numerical Analysis of the Quantum Yield |
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331 | (4) |
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Anomalous Low Temperature Charge Leakage Mechanism in ULSI Flash Memories |
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335 | (4) |
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Deuterium Effect on Interface States and SILC Generation in CHE Stress Conditions: A Comparative Study |
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339 | (4) |
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Highly-reliable Gate Oxide under Fowler-Nordheim Electron Injection by Deuterium Pyrogenic Oxidation and Deuterated Poly-Si Deposition |
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343 | (4) |
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Session 15: Integrated Circuits and Manufacturing-Advanced DRAMs |
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347 | (26) |
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An Orthogonal 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM |
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349 | (4) |
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Highly Manufacturable 4Gb DRAM Using 0.11μm DRAM Technology |
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353 | (4) |
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Diagonal Layout & Surface Strap Trench (DST) cell |
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357 | (4) |
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A Novel Bit-Line Process using Poly-Si Masked Dual-Damascene (PMDD) for 0.13μm DRAMs and Beyond |
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361 | (4) |
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A Fully Working 0.14μm DRAM Technology with Polymetal (W/WNx/Poly-Si) Gate |
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365 | (4) |
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Novel Capacitor Technology for High Density Stand-Alone and Embedded DRAMs |
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369 | (4) |
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Session 16: Quantum Electronics and Compound Semiconductors-GaN and RF Power Devices |
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373 | (24) |
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A 50-W AlGaN/GaN HEMT Amplifier |
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375 | (2) |
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Novel High Drain Breakdown Voltage AlGaN/GaN HFETs using Selective Thermal Oxidation Process |
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377 | (4) |
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Characteristics of AlGaN/GaN HEMT Devices with SiN Passivation |
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381 | (4) |
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Microwave Performance of AlGaN/GaN Metal Insulator Semiconductor Field Effect Transistors |
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385 | (4) |
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Diagnosis of Trapping Phenomena in GaN MESFETs |
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389 | (4) |
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A Low-Distortion 230W GaAs Power FP-HFET Operated at 22V for Cellular Base Station |
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393 | (4) |
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Session 17: Detectors, Sensors and Displays-MEMs and Biochemical Sensors |
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397 | (30) |
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Mechanically Temperature-Compensated Flexural-Mode Micromechanical Resonators |
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399 | (4) |
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Development of a Wide Tuning Range MEMS Tunable Capacitor for Wireless Communication Systems |
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403 | (4) |
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An Active Microelectronic Transducer for Enabling Label-Free Miniaturized Chemical Sensors |
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407 | (4) |
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Organic-Based Transducer for Low-Cost Charge Detection in Aqueous Media |
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411 | (4) |
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CMOS-Only Sensors and Manipulators for Microorganism (Invited) |
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415 | (4) |
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Fingerprint Imager Based on a-Si:H Active-Matrix Photo-Diode Arrays |
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419 | (4) |
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Low Operation Voltage High Integrated Field Emitter Arrays by Transfer Metal Mold Technique Using Ultra Precision Machining and Super Microelectroplating Technology |
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423 | (4) |
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Session 18: Process Technology-Advanced FEOL Technology |
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427 | (22) |
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Ultra Shallow Junction Profiling (Invited) |
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429 | (4) |
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Low Thermal Budget Elevated Source/Drain Technology Utilizing Novel Solid Phase Epitaxy and Selective Vapor Phase Etching |
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433 | (4) |
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Low Temperature (≤800°C) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for sub-70 nm CMOS |
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437 | (4) |
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Laser Thermal Annealed SSR Well Prior to Epi-Channel Growth (LASPE) for 70 nm nFETs |
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441 | (4) |
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Highly Reliable Poly-SiGe/Amorphous-Si Gate CMOS |
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445 | (4) |
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Session 19: CMOS Devices-Mixed Signal and RF CMOS |
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449 | (26) |
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A 140 GHz ft and 60 GHz fmax DTMOS Integrated with High-Performance SOI Logic. Technology |
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451 | (4) |
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CMOS Device Optimization for System-On-a-Chip Applications (Invited) |
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455 | (4) |
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An 1.5 V High Performance Mixed Signal Integration with Indium Channel for 130 nm Technology Node |
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459 | (4) |
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Impact of Process Scaling on 1/f Noise in Advanced CMOS Technologies |
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463 | (4) |
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A.T.A. Zegers-Van Duijnhoven |
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Impact of 0.10μm SOI CMOS with Body-Tied Hybrid Trench Isolation Structure to Break through the Scaling Crisis of Silicon Technology |
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467 | (4) |
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Latchup Immunity and Well Profile Design by a Deep Carbon-Doped Layer |
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471 | (4) |
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Session 20: Solid State Devices-Emerging Wireless Technology |
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475 | (22) |
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A High-Aspect-Ratio Silicon Substrate-Via Technology and Applications: Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation |
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477 | (4) |
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A Micromachining Post-Process Module for RF Silicon Technology |
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481 | (4) |
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On-Chip Wireless Interconnection with Integrated Antennas |
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485 | (4) |
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A High-Q Tunable Micromechanical Capacitor with Movable Dielectric for RF Applications |
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489 | (4) |
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High-Q VHF Micromechanical Contour-Mode Disk Resonators |
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493 | (4) |
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Session 21: Modeling and Simulation-Process Modeling |
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497 | (30) |
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Modeling of Dishing for Metal Chemical Mechanical Polishing |
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499 | (4) |
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Recent Advances in Feature Scale Simulation (Invited) |
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503 | (4) |
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A Physical Model for Implanted Nitrogen Diffusion and Its Effect on Oxide Growth |
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507 | (4) |
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A New Model for {311} Defects Base on In-Situ Measurements |
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511 | (4) |
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Boron Diffusion and Activation in the Presence of Other Species |
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515 | (4) |
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Investigation of a Model for the Segregation and Pile-Up of Boron at the SiO2/Si Interface during the Formation of Ultra-Shallow p+ Junctions |
|
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519 | (4) |
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Modeling of Arsenic Transient Enhanced Diffusion and Background Boron Segregation in Low-Energy As+ Implanted Si |
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523 | (4) |
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Session 22: CMOS and Interconnect Reliability-Breakdown in Thin Oxides |
|
|
527 | (30) |
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The Statistical Distribution of Percolation Resistance as a Probe into the Mechanics of Ultra-thin Oxide Breakdown |
|
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529 | (4) |
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Post Soft Breakdown Conduction in SiO2 Gate Oxides |
|
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533 | (4) |
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Substrate Hole Current Origin after Oxide Breakdown |
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537 | (4) |
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Voltage-Dependent Voltage-Acceleration of Oxide Breakdown for Ultra-thin Oxides |
|
|
541 | (4) |
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Extending the Reliability Scaling Limit of SiO2 through Plasma Nitridation |
|
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545 | (4) |
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Resolving the Non-uniqueness of the Activation Energy Associated with TDDB for SiO2 Thin Films |
|
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549 | (4) |
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Impact of MOSFET Oxide Breakdown on Digital Circuit Operation and Reliability |
|
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553 | (4) |
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Session 23: Integrated Circuits and Manufacturing-High Performance CMOS Logic Technologies |
|
|
557 | (26) |
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|
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A 0.11 μm CMOS Technology with Copper and Very-low-k Interconnects for High-Performance System-On-a Chip Cores |
|
|
559 | (4) |
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A 0.13μm CMOS Technology with 193nm Lithography and Cu/Low-k for High Performance Applications |
|
|
563 | (4) |
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A 130nm Generation Logic Technology Featuring 70nm Transistors, Dual VT Transistors and 6 layers of Cu Interconnects |
|
|
567 | (4) |
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A Versatile 0.13 μm CMOS Platform Technology Supporting High Performance and Low Power Applications |
|
|
571 | (4) |
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A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Applications |
|
|
575 | (4) |
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|
A 2.05 μm2 Full CMOS Ultra-Low Power SRAM Cell with 0.15μm Generation Single Gate CMOS Technology |
|
|
579 | (4) |
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Session 24: Quantum Electronics and Compound Semiconductors-Optoelectronics and Quantum Devices |
|
|
583 | (22) |
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|
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|
|
GaAs Schottky Wrap-Gate Binary-Decision-Diagram Devices for Realization of Novel Single Electron Logic Architecture |
|
|
585 | (4) |
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|
|
Femtosecond All-Optical Devices for Tera-bit/sec Optical Networks (Invited) |
|
|
589 | (4) |
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|
|
Spot-Size-Converted 1.3μm Directly-Modulated Fabry-Perot and Distributed Feedback Lasers Suitable for Passive Alignment and 2.5 Gb/s Operation at 85C |
|
|
593 | (4) |
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High Temperature Operated (∼250 K) Photovoltaic-Photoconductive (PV-PC) Mixed-mode InAs/GaAs Quantum Dot Infrared Photodetector |
|
|
597 | (4) |
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|
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|
|
Room-temperature Memory Operation of AlGaAs/GaAs High Electron Mobility Transistors with InAs Quantum Dots Embedded in the Channel |
|
|
601 | (4) |
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|
Session 25: Detectors, Sensors and Displays- organic Electronics and Displays |
|
|
605 | (26) |
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|
|
Improved External Coupling Efficiency in Organic Light-Emitting Devices on High-Index Substrates |
|
|
607 | (4) |
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|
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|
|
Application of Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin-Film Transistor Technology to Active-Matrix Organic Light-Emitting Diode Displays |
|
|
611 | (4) |
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|
|
High Performance Light Emitting Polymers for Colour Displays (Invited) |
|
|
615 | (4) |
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|
|
Fast Organic Circuits on Flexible Polymeric Substrates |
|
|
619 | (4) |
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|
|
All-Polymer Thin Film Transistors Fabricated by High-Resolution Ink-jet Printing |
|
|
623 | (4) |
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|
|
Fabrication and Characterization of Cathodoluminescent Devices made Using Porous Silicon as a Cold-Cathode Field Emitter |
|
|
627 | (4) |
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|
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Session 26: 2000 IEDM Evening Panel Discussion |
|
|
631 | (2) |
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|
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Session 27: 2000 IEDM Evening Panel Discussion |
|
|
633 | (2) |
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|
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Session 28: Process Technology-Gate Dielectrics-SiON and High-k Dielectrics |
|
|
635 | (22) |
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|
|
Impact of Recoiled-Oxygen-Free Processing on 1.5 nm SiON Gate-Dieletric in Sub-100 nm CMOS Technology |
|
|
637 | (4) |
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|
|
Molybdenum Metal Gate MOS Technology for Post-SiO2 Gate Dielectrics |
|
|
641 | (4) |
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|
Effect of Polysilicon Gate on the Flatband Voltage Shift and Mobility Degradation for ALD-Al2O3 Gate Dielectric |
|
|
645 | (4) |
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|
Conformable Formation of High Quality Ultra-Thin Amorphous Ta2O5 Gate Dielectrics Utilizing Water Assisted Deposition (WAD) for Sub 50 nm Damascene Metal Gate MOSFETs |
|
|
649 | (4) |
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High-K Gate Dielectrics with Ultra-low Leakage Current Based on Praseodymium Oxide |
|
|
653 | (4) |
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|
Session 29-CMOS Devices-Novel Devices and Device Physics |
|
|
657 | (30) |
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|
A Notched Metal Gate MOSFET for sub-0.1 μm Operation |
|
|
659 | (4) |
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|
Dynamic Threshold Voltage Damascene Metal Gate MOSFET (DT-DMG-MOS) with Low Threshold Voltage, High Drive Current, and Uniform Electrical Characteristics |
|
|
663 | (4) |
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A Novel SiGe-Inserted SOI Structure for High Performance PDSOI CMOSFETs |
|
|
667 | (4) |
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Low Field Mobility of Ultra-Thin SOI N- and P-MOSFETs: Measurements and Implications on the Performance of Ultra-Short MOSFETs |
|
|
671 | (4) |
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|
Role of Inversion Layer Quantization on Sub-Bandgap Impact Ionization in Deep-Sub-Micron n-channel MOSFETs |
|
|
675 | (4) |
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Edge Hole Direct Tunneling in Off-State Ultrathin Gate Oxide p-Channel MOSFETs |
|
|
679 | (4) |
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A Novel, Aerosol-Nanocrystal Floating-Gate Device for Non-Volatile Memory Applications |
|
|
683 | (4) |
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Session 30: Detectors, Sensors and Displays-Sensors for Imaging |
|
|
687 | (26) |
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Sensitivity Improvements in Progressive-Scan FT-CCDs for Digital Still Camera Applications |
|
|
689 | (4) |
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A Novel Lateral Overflow Drain Technology for High Quantum Efficiency CCD Imagers |
|
|
693 | (4) |
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|
Monolithic 3.3V CCD/SOI-CMOS Imager Technology |
|
|
697 | (4) |
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High Sensitivity and No-Cross-Talk Pixel Technology for Embedded CMOS Image Sensor |
|
|
701 | (4) |
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High Performance 0.25-μm CMOS Color Imager Technology with Non-silicide Source/Drain Pixel |
|
|
705 | (4) |
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Ultraviolet Avalanche Photodiode in CMOS Technology |
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|
709 | (4) |
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Session 31: Modeling and Simulation-Advanced Device and Interconnect Simulation |
|
|
713 | (22) |
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The Ballistic Nanotransistor: A Simulation Study |
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|
715 | (4) |
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Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs |
|
|
719 | (4) |
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Advanced Model and Analysis for Series Resistance in Sub-100nm CMOS Including Poly Depletion and Overlap Doping Gradient Effect |
|
|
723 | (4) |
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Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs |
|
|
727 | (4) |
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|
RLC Signal Integrity Analysis of High-Speed Global Interconnect |
|
|
731 | (4) |
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Session 32: Solid State Devices-RF Analog and High-Speed Mixed Signal Si Device Technologies |
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735 | (26) |
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Device and Technology Requirements for Next Generation Communications Systems (Invited) |
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737 | (4) |
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A 0.2-μm 180-GHz-fmax 6.7-ps-ECL SOI/HRS Self-Aligned SEG SiGe HBT/CMOS Technology for Microwave and High-Speed Digital Applications |
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741 | (4) |
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SiGe Bipolar Technology for Mixed Digital and Analogue RF Applications |
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745 | (4) |
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Novel Epitaxial p-Si/n-Si1-yCy/p-Si Heterojunction Bipolar Transistors |
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749 | (4) |
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Enhanced Performance in Sub-100nm CMOSFETs Using Strained Epitaxial Silicon-Germanium |
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753 | (4) |
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High Performance Digital-Analog Mixed Device on a Si Substrate with Resistivity Beyond 1 kΩ cm |
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757 | (4) |
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Session 33: Integrated Circuits and Manufacturing-Non-Volatile Memory Technology |
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761 | (26) |
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Advanced Flash Memory Technology and Trends for File Storage Application (Invited) |
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763 | (4) |
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A 0.15μm NAND Flash Technology with 0.11 μm2 Cell Size for 1 Gbit Flash Memory |
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767 | (4) |
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A Novel Surface-Oxidized Barrier-SiN Cell Technology to Improve Endurance and Read-Disturb Characteristics for Gigabit NAND Flash Memories |
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771 | (4) |
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High-Density (4.4F2) NAND Flash Technology Using Super-Shallow Channel Profile (SSCP) Engineering |
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775 | (4) |
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A Novel Uniform-Channel-Program-Erase (UCPE) Flash EEPROM Using An Isolated P-well Structure |
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779 | (4) |
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64Kbit CMVP FeRAM Macro with Reliable Retention/Imprint Characteristics |
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783 | (4) |
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Session 34: Process Technology-Memory Technologies |
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787 | (18) |
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Conformal CVD-Ruthenium Process for MIM Capacitor in Giga-bit DRAMs |
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789 | (4) |
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Liner-Supported Cylinder (LSC) Technology to Realize Ru/Ta2O5/Ru Capacitor for Future DRAMs |
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793 | (4) |
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Low Thermal-Budget Fabrication of Sputtered-PZT Capacitor on Multilevel Interconnects for Embedded FeRAM |
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797 | (4) |
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A Novel Ir/IrO2/Pt-PZT-Pt/IrO2/Ir Capacitor for A Highly Reliable Mega-Scale FRAM |
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801 | (4) |
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Session 35: Modeling and Simulation-Compact Modeling |
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805 | (22) |
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RF-Distortion in Deep-Submicron CMOS Technologies |
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807 | (4) |
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The Equivalence of van der Ziel and BSIM4 Models in Modeling the Induced Gate Noise of MOSFETs |
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811 | (4) |
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BSIM4 Gate Leakage Model Including Source-Drain Partition |
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815 | (4) |
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The Construction and Evaluation of Behavioral Models for Microwave Devices Based on Time-Domain Large-Signal Measurements |
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819 | (4) |
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A New Analytical Delay and Noise Model for On-Chip RLC Interconnect |
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823 | (4) |
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Session 36: Integrated Circuits and Manufacturing-Manufacturing and Yield |
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827 | |
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Phase Shift Lithography in the Manufacture of sub-120 nm Low-Voltage DSP Circuits (Invited) |
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829 | |
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Throughput Enhancement Strategy of Maskless Electron Beam Direct Writing for Logic Device |
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833 | |
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Impact of Gate-Induced Drain Leakage Current on the Tail Distribution of DRAM Data Retention Time |
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837 | |
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Yield Management Methodology for SoC Vertical Yield Ramp |
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841 | |
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New Yield Models for DSM Manufacturing |
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845 | |
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Session 7: Integrated Circuits and Manufacturing-Analog/RF and 3D ICs |
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Cu Single Damascene Interconnects with Plasma-Polymerized Organic Polymers (k=2.6) for High-Speed, 0.1μm CMOS Devices |
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851 | |
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Session 8: Quantum Electronics and Compound Semiconductors-High Speed Compound Semiconductor Devices |
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Undoped-Emitter InP/InGaAs HBTs for High-Speed and Low-Power Applications |
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854 | |
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Session 9: Detectors, Sensors and Displays-Si Thin Film Transistors |
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A Novel Implantless MOS Thin-Film Transistor with Simple Processing, Excellent Performance and Ambipolar Operation Capability |
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857 | |
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Session 10: CMOS Devices-Device Scaling |
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Very High Performance 40nm CMOS with Ultra-Thin Nitride/Oxynitride Stack Gate Dielectric and Pre-Doped Dual Poly-Si Gate Electrodes |
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860 | |
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Session 13: Solid State Devices-Nanoelectronics |
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Room-Temperature Operation of Multifunctional Single-Electron Transistor Logic |
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863 | |
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Silicon Single-Electron CCD, A. Fujiwara and Y. Takahashi |
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866 | |
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Session 18: Process Technology-Advanced FEOL Technology |
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Stencil Mask Ion Implantation Technology for High Performance MOSFETs |
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869 | |
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