The International Integrated Reliability Workshop provides a forum for sharing new approaches to achieve and maintain microelectronic component reliability. Topics reproduced in this volume include: BIR - breaking down barriers; and shear test for adhesion measurement of small structures.
Foreword v KEYNOTE ADDRESS Benchmarking Semiconductor Manufacturing 1(6) Professor D.A. Hodges TECHNICAL PRESENTATIONS 7(112) Resistance Transients in Thin-film Noise Data 7(6) L.M. Head Plasma-Induced Polarity Dependent Hot-Carrier Response of CMOS Devices Across a Wafer 13(3) V.K. Janapaty B. Bhuva S. Kerns N. Bui Acceleration Factors of PMOS Hot-Carrier Degradation 16(6) H. Katto Investigation of the Intrinsic SiO(2) Area Dependence using TDDB Testing 22(4) J.G. Prendergast N. Finucane J.S. Suehle Antenna Damage from a Plasma TEOS Deposition Reactor: Relationship with Surface Charge and RF Sensor Measurements 26(5) I.J. Gupta K. Taylor D. Buck S. Krishnan Optimized Application of Antenna Structures in a WLR Monitoring Program 31(4) J. Fazekas W. Asam J. von Hagen CMOS Transistor Reliability and Performance Impacted by Gate Microstructure 35(7) B. Yu D.-H. Ju N. Kepler T.-J. King C. Hu Designing-in Device Reliability during the Development of High-Performance CMOS Logic Technology 0.13 um 42(3) D.K. Nayak M.-Y. Hao R.S. Hijab HCI Lifetime Enhancement by Double Implanted S/D (DISD) of Nch MOSFET in 0.25 um CMOS Technology 45(2) D. Wu S. Luning D.H. Ju N. Kepler Effect of Electronic Corrections on the Thickness Dependence of Thin Oxide Reliability 47(3) G.B. Alers A.S. Oates D.K. Monroe K.S. Krisch B.E. Weir The Non-uniqueness of Breakdown Distributions in Silicon Oxides 50(6) J.C. Jackson O. Oralkan T. Robinson D.J. Dumin G.A. Brown Temperature Dependence of Gate Current in Ultra Thin SiO(2) in Direct-Tunneling Regime 56(6) A. Yassine R.S. Hijab Charge-to-Breakdown and Trap Generation Process in Thin Oxides 62(5) G. Bersuker J. Werking D.Y. Chan A New Technique to Extract TDDB Acceleration Parameters from Fast Qbd Tests 67(3) Y. Chen J.S. Suehle C.C. Shen J. Bernstein C.R. Messick Correlation of Charge to Breakdown Obtained from Constant Current Stresses and Ramped Current Stresses, and the Implications for Ultra-Thin Gate Oxides 70(5) N.A. Dumin A Candid Comparison of the SWEAT Technique & the Conventional Test Procedure for Electromigration Study in Sub-Half Micron ULSI Interconnects 75(5) S.S. Menon R.K. Choudhury High Resolution Electromigration Measurements for Reduction of the Test Time 80(6) C. de Keukeleire L. Tielemans P. De Pauw A Novel In-process Wafer-Level Screening Technique for CMOS Devices 86(6) I. Yoshii K. Hama H. Hazama H. Kamijo Y. Ozawa Pulsed BTS -- an Accurate and Fast Technique to Determine Mobile Ion Concentrations in Gate and Field Oxides 92(5) L. Gutai Charge Pumping for DRAM Retention Diagnostics 97(6) J.W. Adkisson R. Divakaruni J. Slinkman Automated Extraction of Parasitic BJTs for CMOS I/O Circuits Under ESD Stress 103(7) T. Li Y. Huh S. Kang Evolution of BSIM3v3 Parameters During Hot-Carrier Stress 110(9) S. Minehane P. OSullivan A. Mathewson B. Mason DISCUSSION GROUP SUMMARY REPORTS 119(7) Designing in Reliability 119(2) M.W. Poulter W.J. Vigrass Wafer-Level Reliability 121(2) C.R. Messick S.J. Yankee Customer Reliability Requirements 123(2) I. Wylie A. Preussger Reliability Test Structures 125(1) T.E. Turner J.R. Lloyd POSTER PRESENTATIONS 126(19) A Practical Statistical Technique to Improve Seal Integrity and Reliability of Microelectronic Packages 126(2) T.R. Narasimhan E.H. Trotter Automated Analysis of MOS-C Relaxation Time for WLR Testing 128(2) D.K. Monroe S.E. Swanson A New Algorithim for Circuit-Level Electrothermal Simulation under EOS/ESD Stress 130(2) T. Li C.H. Tsai Y.J. Huh E. Rosenbaum S.M. Kang Study on the Al/Silicon Rich Oxide/Si Structure as a Surge Suppresser 132(2) M. Aceves J. Pedraza J. Apolinar Reynoso-Hernandez C. Falcony W. Calleja Transformation of Charge-to-Breakdown Obtained from Ramped Current Stresses into Charge-to-Breakdown and Time-to-Breakdown Domains for Constant Current Stress 134(2) N.A. Dumin Isothermal versus Standard Wafer Electromigration Test for the Characterization of Metal Systems 136(2) D.J. Brisbin T.E. Turner Confirmation of a Predictive Process Dependent Model of Oxide Charging 138(2) J.F. Conley, Jr. Q(bd) Dependence on Stress and Test Structure Parameters: A Review 140(2) A. Martin P. OSullivan A. Mathewson Degradation of the Characteristics of p+ poly MOS Capacitors with NO Nitrided Gate Oxide Due to Post Nitrogen Annealing 142(2) M.K. Mazumder A. Teramoto K. Kobayashi M. Sekine S. Kawazu H. Koyama Reliability Test Chips: NIST 33 & NIST 34 for JEDEC Inter-Laboratory Experiments and More 144(1) H.A. Schafft TUTORIALS 145(8) Abstract of Tutorial A: Determination of Physical Parameters and Reliability of Ultra Thin Oxides 145(1) E.A. Cartier Abstract & Summary of Tutorial B: Device Design Methodology and Reliability Strategy for Deep Submicron Technology 146(7) R. Divakaruni B. El Kareh W. R. Tonti BIOGRAPHIES 153
