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International Integrated Reliability Workshop 1998 [Pehme köide]

  • Formaat: Paperback / softback, 176 pages, kõrgus x laius: 279x216 mm
  • Ilmumisaeg: 01-Mar-1998
  • Kirjastus: I.E.E.E.Press
  • ISBN-10: 0780348818
  • ISBN-13: 9780780348813
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  • Formaat: Paperback / softback, 176 pages, kõrgus x laius: 279x216 mm
  • Ilmumisaeg: 01-Mar-1998
  • Kirjastus: I.E.E.E.Press
  • ISBN-10: 0780348818
  • ISBN-13: 9780780348813
Teised raamatud teemal:
The International Integrated Reliability Workshop provides a forum for sharing new approaches to achieve and maintain microelectronic component reliability. Topics include: contributors to failure; waver level reliability; building in reliability; and reliability test structures.
Foreword v Keynote Address Semiconductor Equipment Industry: Migration from equipment to entire process module solutions vi Dennis Yost TECHNICAL PRESENTATIONS Thermal Conductance of IC Interconnects Embedded in Dielectric 1(9) J.P. Gill T.D. Sullivan D.L. Harmon Wafer Level Electromigration Applied to Advance Copper/Low k Dielectric Process Sequence Integration 10(6) Donald Pierce James Educato Viren Rana Dennis Yost Wafer Level Monitoring and Process Optimization for Robust Via EM Reliability 16(3) T. Zhao C. Shih J. McCollum F. Hawley F. Issaq B. Cronquist R. Lambertson E. Hamdy Z. Yang C. Chern M. Liao G. Say G. Koh L. Chan R. Sundaresan A Study of Stress Voiding Effect on A1Si Metal Bank Allowed Lifetime for a IC Foundry Fabs 19(4) K.P. Lin C.D. Chang K.S. Huang S.L. Hsu A Study of Field Dependence of TDDB of Ultra-Thin Gate Oxide and Anomaly in the I-V of MOS Devices with Active Guard Ring 23(4) Abdullah Yassine Homi Nariman Kola Olasupo Laura Govea Practical Triggering of Early Breakdown in Thin Oxides 27(6) J.C. Jackson D.J. Dumin Cleston Messick Complete method for Ebd Correction by Series Resistance Characterization 33(6) David K. Monroe Scot E. Swanson A Constant Gate Current Technique for Obtaining Low-Frequency C-V Characteristics of MOS Capacitors 39(6) Jack G. Qian Roy A. Hensley Eric Littlefield The Life Time Model using the Correlation between Dielectric Thickness, and Voltage Stress for 64MB Accelerated Reliability Testing 45(4) Yumi Kwon Namhyun Cha Samjin Whang Namsung Cho Whajoon Lee Electric Field and Temperature Acceleration of Quasi-Breakdown Phenomena in Ultrathin Oxides 49(6) D. Roy S. Bruyere E. Vincent G. Ghibaudo A Comprehensive Physical Model of Oxide Wearout and Breakdown Involving Trap Generation, Charging and Discharging 55(7) D. Qian D.J. Dumin A Preliminary Investigation of the Kinetics of Post-Oxidation Anneal Induced E-Precursor Formation 62(6) J.F. Conley, Jr. W.F. McArthur P.M. Lenahan A New Mechanism for Gate Oxide Degradation 68(4) Chuan H. Liu Thomas A. DeMassa Julian J. Sanchez ESD Technology Benchmarking for Evaluation of Electrostatic Discharge Robustness of CMOS Technologies 72(6) S. Voldman W. Anderson R. Ashton M. Chaine C. Duvvury T. Maloney E. Worley Non-Contact In-Line Monitoring of Plasma-Induced Latent Damage 78(4) Tim Turner Steve Weinzierl Monitoring Charging in High Current Ion Implanters Yields Optimum Preventive Maintenance Schedules and Procedures 82(4) Henry Gonzalez Steven Reno Cleston Messick Wes Lukaszek Thomas Romanski Characterizing Electron Shower with CHARM-2 wafers on Eaton NV-8200P Medium Current Ion Implanter 86(4) Steve Reno Henry Gonzalez Cleston Messick Wes Lukaszek David A. St. Angelo Klaus Becker Bobby Rogers DISCUSSION GROUP SUMMARY REPORTS Interconnect Reliability---with a Focus on Copper: 90(2) T. Sullivan D. Pierce Oxides---Ultra Thin Oxides: 92(2) R.P. Vollertsen D.J. Dumin Electrostatic Discharge---ESD: 94(3) H. Gieser E. Worley C-V Measurements - and Its Implication on Oxide, Transistor, and Non-Volatile Memory Cell Reliability: 97(2) U. Schwalke B. Gordon POSTER PRESENTATIONS Investigation of Initial Charge Trapping and Oxide Breakdown under Fowler-Nordheim Injection 99(6) A. Martin Equilibrium Controlled Static C-V Method and Its Application 105(2) U. Schwalke C. Gruensfelder M. Kerber Investigation on the Reduction of the Dark Current for PIN Silicon Photodiodes Using Statistical Methods 107(2) M. Aceves P. Rosales A. Cerdeira M. Estrada A. E. Cabal J. Ramirez Interconnect Reliability Test Chip NIST 36: for Development of Measurement Tools and Standards 109(3) H.A. Schafft Characterization of Quasi-Breakdown in Ultra-Thin Gate Oxides in an Automated Test Environment 112(24) D. Brisbin TUTORIALS Summary of Tutorial 1: The Analysis of Oxide Reliability Data 114(21) W.R. Hunter Abstract of Tutorial 2: Reliability Issues and the Development of Advanced DRAM Products 135(1) W. Ellis Biographies 136(2) Special Interest Groups (SIGs) Report 138