These conference proceedings examine such topics as: power efficient digital circuits and technologies; algorithmic and systems issues; mixed signal design; architecture and memory design; digital logic; and synthesis and optimization.
Committee List xi Opening and Welcome David Blaauw Enrico Macii Keynote Speech Transmetas Crusoe: Low-Power x86-Compatible Microprocessors Built with Software xiii David R. Ditzel E. Macii Invited Talk 1 Low-Power Micromachined Microsystems 1(8) Khalil Najafi D. Blaauw Power Efficient Digital Circuits and Technologies I B. Athas J. Burr Design Issues for Dynamic Voltage Scaling 9(304) Thomas D. Burd Robert W. Brodersen Dual-VT SRAM Cells with Full-Swing Single-Ended Bit Line Sensing for High-Performance On-Chip Cache in 0.13 μm Technology Generation 15(5) Faith Hamzaoglu Yibin Ye Ali Keshavarzi Kevin Zhang Siva Narendra Shekhar Borkar Vivek De Mircea Stan An Adaptive On-Chip Voltage Regulation Technique for Low-Power Applications 20(5) Nicola Dragone Akshay Aggarwal, L. Richard Carley Robust Ultra-Low Power Sub-threshold DTMOS Logic 25(6) Hendrawan Soeleman Kaushik Roy Bipul Paul Algorithmic and Systems Issues M. Martonosi K. Usami Algorithmic Transforms for Efficient Energy Scalable Computation 31(6) Amit Sinha Alice Wang Anantha P. Chandrakasan Operating-System Directed Power Reduction 37(6) Yung-Hsiang Lu Giovanni De Micheli Luca Benini Energy Minimization with Guaranteed Quality of Service 43(6) Gang Qu Miodrag Potkonjak Energy Efficient Design of Portable Wireless Systems 49(6) Tajana Simunic Haris Vikalo Peter Glynn Giovanni De Micheli Mixed Signal Design M. Pelgrom S. Mukherjee Power Consumption Reduction in High-Speed ΣΔ Bandpass Modulators 55(6) P. Cusinato F. Stefani A. Baschirotto Low Power Mixed Analog-Digital Signal Processing 61(6) Mattias Duppils Christer Svensson A Low-Power Clock and Data Recovery Circuit for 2.5 Gb/s SDH Receivers 67(6) Andrea Pallotta Francesco Centurelli Alessandro Trifiletti A Micro-Power Mixed Signal IC for Battery-Operated Burglar Alarm Systems 73(5) Silvio Bolliri Luigi Raffo Paolo Porcu Architecture and Memory Design B. Moyer C. Piguet A Recursive Algorithm for Low-Power Memory Partitioning 78(6) Luca Benini Alberto Macii Massimo Poncino Optimization of High-Performance Superscalar Architectures for Energy Efficiency 84(6) V. Zyuban P. Kogge Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories 90(6) Michael Powell Se-Hyun Yang Babak Falsafi Kaushik Roy T. N. Vijaykumar Voltage Scheduling in the IpARM Microprocessor System 96(6) Trevor Pering Thomas Burd Robert Brodersen Digital Logic V. Germini D. Garrett MOS Current Mode Logic for Low Power, Low Noise CORDIC Computation in Mixed-Signal Environments 102(6) Jason M. Musicer Jan Rabaey Noise-Aware Power Optimization for On-Chip Interconnect 108(6) Ki-Wook Kim Seong-Ook Jung Sung-Mo Kang Unni Narayanan C. L. Liu New Clock-Gating Techniques for Low-Power Flip-flops 114(6) A. G. M. Strollo E. Napoli D. De Caro An Improved Pass Transistor Synthesis Method for Low Power, High Speed CMOS Circuits 120(5) Tudor Vinereanu Sverre Lidholm Synthesis and Optimization D. Marculescu M. Poncino Achieving Utility Arbitrarily Close to the Optimal with Limited Energy 125(6) Gang Qu Miodrag Potkonjak Power Minimization of Functional Units by Partially Guarded Computation 131(6) Junghwan Choi Jinhwan Jeon Kiyoung Choi Systematic Cycle Budget versus System Power Trade-off: a New Perspective on System Exploration of Real-Time Data-Dominated Applications 137(6) Erik Brockmeyer Arnout Vandecappelle Francky Catthoor Low Power Sequential Circuit Design by Using Priority Encoding and Clock Gating 143(6) Xunwei Wu Massoud Pedram Evening Panel Do Our Low-Power Tools Have Enough Horse Power? 149(2) Giovanni De Micheli Tony Correale Hugo De Man Pietro Erratico Jerry Frankil Srini Raghvendra Vivek Tiwari Invited Talk 2 Low-Power Considerations in the Design of Bluetooth 151(4) Sven Mattisson T. Gabara Power Efficient Digital Circuits and Technologies II K. Roy B. Barton High-Speed Dynamic Logic Styles for Scaled-Down CMOS and MTCMOS Technologies 155(6) Mohamed W. Allam Mohab H. Anis Mohamed I. Elmasry A Three-Port nRERL Register File for Ultra-Low-Energy Applications 161(6) Jun-Ho Kwon Soo-Ik Chae Joonho Lim Minimum Power And Area N-Tier Multilevel Interconnect Architectures Using Optimal Repeater Insertion 167(6) Raguraman Venkatesan Jeffrey A. Davis Keith A. Bowman James D. Meindl Practical Considerations of Clock-Powered Logic 173(6) William Athas Modeling and Simulation V. Tiwari M. Nemani Model and Analysis for Combined Package and On-Chip Power Grid Simulation 179(6) Rajendran Panda David Blaauw Rajat Chaudhry Vladimir Zolotov Brian Young Ravi Ramaraju Cycle-Accurate Energy Consumption Measurement and Analysis: Case Study of ARM7TDMI 185(6) Naehyuck Chang Kwanho Kim Hyung Gyu Lee Speeding up Power Estimation of Embedded Software 191(6) Akshaye Sama J. F. M. Theeuwen M. Balakrishnan High-Level Power Estimation with Interconnect Effects 197(6) Kavel M. Buyuksahin Farid N. Najm Poster Session 1 W. Troutman A. Chandrakasan ``Cool Low Power 1 GHz Multi-Port Register File and Dynamic Latch in 1.8 V, 0.25 μm SOI and Bulk Technology 203(4) R. V. Joshi W. Hwang S. C. Wilson C. T. Chuang Low-Power Digital Filtering Using Multiple Voltage Distribution and Adaptive Voltage Scaling 207(3) Sandeep Dhar Dragan Maksimovic Low Power Self-Timed Radix-2 Division 210(3) Jae-Hee Won Kiyoung Choi A Rate Selection Algorithm for Quantized Undithered Dynamic Supply Voltage Scaling 213(3) Lama H. Chandrasena Michael J. Liebelt Low-Power Sensing and Digitization of Cardiac Signals based on Sigma-Delta Conversion 216(3) Andrea Gerosa Arianna Novo Andrea Neviani A 1.5V Low-Power Third Order Continuous-Time Lowpass ΣΔ A/D Converter 219(3) Friedel Gerfers Yiannos Manoli Design of A Low-Power CMOS Baseband Circuit for Wideband CDMA Testbed 222(3) Chunlei Shi Yue Wu Mohammed Ismail Withdrawn A Low-Voltage CMOS Multiplier for RF Applications 225(3) Carl James Debono Franco Maloberti Joseph Micallef Poster Session 2 G. Stamoulis R. Panda Voltage Dependent Gate Capacitance and its Impact in Estimating Power and Delay of CMOS Digital Circuits with Low Supply Voltage 228(3) Koichi Nose Takayasu Sakurai Soo-Ik Chae Reducing Energy Requirements for Instruction Issue and Dispatch in Superscalar Microprocessors 231(3) Kanad Ghose Low Power Synthesis of Sum-of-Products Computation 234(4) K. Masselos S. Theoharis P. K. Merakos T. Stouraitis C. E. Goutis A Spatially-Adaptive Bus Interface for Low-Switching Communication 238(3) Andrea Acquaviva Riccardo Scarsi A Low Power Unified Cache Architecture Providing Power and Performance Flexibility 241(3) Afzal Malik Bill Moyer Dan Cermak Memory System Energy: Influence of Hardware-Software Optimizations 244(3) G. Esakkimuthu N. Vijaykrishnan M. Kandemir M. J. Irwin Energy-efficient Code Generation for DSP56000 family 247(3) Sathishkumar Udayanarayanan Chaitali Chakrabarti Power-Optimal Encoding for DRAM Address Bus 250(3) Wei-Chung Cheng Massoud Pedram Profile-Driven Code Execution for Low Power Dissipation 253(3) Diana Marculescu Synthesis and Optimization V. De D. Xanthopoulus An Asynchronous Matrix-Vector Multiplier for Discrete Cosine Transform 256(6) Kyeounsoo Kim Peter A. Beerel Youpyo Hong Low Power Techniques and Design Tradeoffs in Adaptive FIR Filtering for PRML Read Channels 262(6) Khurram Muhammad Robert B. Staszewski Poras T. Balsara Energy-Efficient 32 x 32-bit Multiplier in Tunable Near-Zero Threshold CMOS 268(5) Vjekoslav Svilan Masataka Matsui James B. Burr RF Design S. Heine Q. Huang Tradeoffs and Design of an Ultra Low Power UHF Transceiver Integrated in a Standard Digital CMOS Process 273(6) Alain-Serge Porret Thierry Melly E. A. Vittoz C. C. Enz An 8mA, 3.8dB NF, 40dB gain CMOS Front-End for GPS Applications 279(5) F. Svelto S. Deantoni G. Montagna R. Castello Bias Boosting Technique for a 1.9GHz Class AB RF Amplifier 284(5) Tirdad Sowlati Sifen Luo Analysis and Design of Low-Phase-Noise Ring Oscillators 289(6) Liang Dai Ramesh Harjani Embedded Tutorial 1 Reliable Low-Power Design in the Presence of Deep Submicron Noise 295(8) Naresh Shanbhag Krishnamurthy Soumyanath Samuel Martin N. Sivan Embedded Tutorial 2 Low-Power DSP for Wireless Communications 303(10) Ingrid Verbauwhede Chris Nicol L. Benini Author Index 313
