A March 2004 symposium brought together industry practitioners and academics engaged in deep sub-micron integrated circuit design and development. Papers from the symposium span numerous disciplines that define the integrated circuit industry. A tutorial section addresses topics related to compact modeling and analysis for nanometer-scale CMOS design. Contributed papers are grouped in sections on physical design migration, CMOS device and memory, printability, package design and interaction, test generation and application, interconnect, analysis and prevention of substrate noise, analysis of variations, analog testing, DFM design, delay test issues, and circuit design trends in DSM. Some specific subjects examined include predicting interconnect uncertainty with a new robust model order reduction method, a versatile high-speed bit error rate testing scheme, and rewiring for watermarking digital circuits. There is no subject index. Annotation ©2004 Book News, Inc., Portland, OR (booknews.com)
