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Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications Unabridged edition [Kõva köide]

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  • Formaat: Hardback, 270 pages
  • Ilmumisaeg: 31-Jan-2021
  • Kirjastus: Artech House Publishers
  • ISBN-10: 1630817937
  • ISBN-13: 9781630817930
Teised raamatud teemal:
Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications Unabridged editionSuurem pilt
  • Formaat: Hardback, 270 pages
  • Ilmumisaeg: 31-Jan-2021
  • Kirjastus: Artech House Publishers
  • ISBN-10: 1630817937
  • ISBN-13: 9781630817930
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781630817930.html
Märksõnad:
Real-time testing and simulation of open- and closed-loop radio frequency (RF) systems for signal generation, signal analysis and digital signal processing require deterministic, low-latency, high-throughput capabilities afforded by user reconfigurable field programmable gate arrays (FPGAs). This comprehensive book introduces LabVIEW FPGA, provides best practices for multi-FPGA solutions, and guidance for developing high-throughput, low-latency FPGA based RF systems. Written by a recognized expert with a wealth of real-world experience in the field, this is the first book written on the subject of FPGAs for radar and other RF applications.



The companion website for this book can be found at https://github.com/LVFPGABOOK/
Preface 11(4)
Acknowledgments 15(4)
Chapter 1 Introduction
19(22)
1.1 What Is an FPGA?
19(1)
1.2 History of FPGAs
20(1)
1.2.1 Evolution of FPGA Tools
21(1)
1.3 Selecting an FPGA
21(3)
1.3.1 Build Your Own Board Approach
22(1)
1.3.2 FPGA Platform Approach
23(1)
1.3.3 Selecting FPGA Pros and Cons
23(1)
1.4 Why Lab VIEW FPGA?
24(3)
1.4.1 Lab VIEW FPGA Hardware
24(1)
1.4.2 Lab VIEW FPGA Math and Logic
25(2)
1.4.3 Lab VIEW FPGA Interfacing to the Host Computer
27(1)
1.5 The Development Process
27(8)
1.5.1 Risk Analysis
29(1)
1.5.2 Estimates
30(1)
1.5.3 Requirements Management
30(1)
1.5.4 Source Code Control
30(1)
1.5.5 Bug and Task Tracking
31(1)
1.5.6 Document Management
32(1)
1.5.7 Automated Builds
33(1)
1.5.8 Technical Debt
33(1)
1.5.9 Laboratory Information Management System
34(1)
1.5.10 Development Process Conclusion
35(1)
1.6 Book Overview
35(6)
1.6.1
Chapter 2: How to Learn Lab VIEW FPGA
36(1)
1.6.2
Chapter 3: Background Technology
36(1)
1.6.3
Chapter 4: Lab VIEW FPGA
36(1)
1.6.4
Chapter 5: Lab VIEW FPGA RF Case Studies
36(1)
1.6.5
Chapter 6: Looking Ahead
36(1)
References
37(4)
Chapter 2 How to Learn Lab VIEW FPGA
41(16)
2.1 Learning Lab VIEW FPGA Versus VHDL/Verilog
42(1)
2.2 Preconceived Notions
43(2)
2.3 Four Stages of Competence
45(1)
2.4 Lab VIEW FPGA Learning Phases
45(4)
2.4.1 Have a Problem to Solve
45(2)
2.4.2 Software Model
47(1)
2.4.3 Software Engineering
47(1)
2.4.4 Lab VIEW Proficiency
48(1)
2.4.5 FPGA Knowledge
48(1)
2.4.6 Lab VIEW FPGA Learning Phases Conclusion
49(1)
2.5 Users of Lab VIEW FPGA
49(4)
2.5.1 Existing Lab VIEW Developer
49(1)
2.5.2 Non-Lab VIEW Software Developer
50(1)
2.5.3 VHDL/Verilog Developer
51(1)
2.5.4 Algorithm Expert
52(1)
2.5.5 RF, Radar, and EW Subject Matter Expert
52(1)
2.5.6 Management
52(1)
2.6 Summary
53(4)
References
53(4)
Chapter 3 Background Technology
57(22)
3.1 Introduction
57(1)
3.2 History of FPGAs
58(3)
3.2.1 Before FPGAs
58(1)
3.2.2 Earlier FPGAs
58(1)
3.2.3 Math/Digital Signal Processing Capability
59(1)
3.2.4 The Specialization of FPGAs
59(2)
3.3 Inside an FPGA
61(4)
3.3.1 Electronics Kit Analogy
61(2)
3.3.2 Logic Blocks
63(1)
3.3.3 Interconnects
63(1)
3.3.4 I/O
63(1)
3.3.5 Clocks
64(1)
3.3.6 Math on an FPGA
64(1)
3.3.7 Memory on an FPGA
65(1)
3.4 Benefits of FPGAs
65(2)
3.4.1 Determinism
66(1)
3.4.2 Low Latency
66(1)
3.4.3 Parallelism
67(1)
3.4.4 High Throughput
67(1)
3.5 Industries and Applications
67(4)
3.6 Compared to ASICs, CPUs, and GPUs
71(3)
3.6.1 ASICs
71(1)
3.6.2 CPUs
71(2)
3.6.3 GPUs
73(1)
3.7 Summary
74(5)
References
74(5)
Chapter 4 Using Lab VIEW FPGA
79(90)
4.1 Overview
79(1)
4.2 A Systems Engineering Approach
80(6)
4.2.1 Development Models
81(1)
4.2.2 Requirements Gathering
82(1)
4.2.3 Design
83(2)
4.2.4 Minimum Viable Product
85(1)
4.2.5 Risk Analysis
85(1)
4.3 Generic Lab VIEW FPGA Systems View
86(1)
4.4 Lab VIEW Environment
87(11)
4.4.1 Setting Up Lab VIEW
88(1)
4.4.2 Lab VIEW File Types
89(3)
4.4.3 Example Finder
92(2)
4.4.4 Context Help
94(1)
4.4.5 Tools Options
94(1)
4.4.6 Lab VIEW Quick Drop
95(1)
4.4.7 Lab VIEW Bookmarks
95(1)
4.4.8 Separate Source and Compiled Lab VIEW Code
96(1)
4.4.9 Reentrancy in Lab VIEW Vis
96(1)
4.4.10 What Is a sub VI?
97(1)
4.4.11 Polymorphic Vis
97(1)
4.4.12 Object-Oriented Design in Lab VIEW
97(1)
4.5 Host Computer Functionalities and Interfacing
98(19)
4.5.1 Host to or from the FPGA
98(13)
4.5.2 To and From the VST
111(1)
4.5.3 P2P Configurations
111(1)
4.5.4 MGT Configurations
112(1)
4.5.5 Disk Interfacing
113(2)
4.5.6 Interfacing to Many FPGA Cards
115(2)
4.5.7 Host Interfacing Conclusion
117(1)
4.6 Inside the FPGA
117(30)
4.6.1 To and From the FPGA
118(12)
4.6.2 Inside the FPGA
130(17)
4.7 Simulating the Design
147(4)
4.7.1 Simulation Modes
148(2)
4.7.2 Simulation Example
150(1)
4.7.3 Simulation Summary
150(1)
4.8 Compiling the FPGA VI
151(9)
4.8.1 Compiling an FPGA
151(1)
4.8.2 Lab VIEW FPGA Compile Steps
152(1)
4.8.3 Xilinx Compile Tools
153(1)
4.8.4 Compile Locations
154(1)
4.8.5 Compilation Hardware Considerations
154(1)
4.8.6 Simultaneous Compiles
155(1)
4.8.7 Multiple Compiles of the Same FPGA VI
155(1)
4.8.8 Compile Failures
156(3)
4.8.9 Periodic Compile Checks
159(1)
4.8.10 Guidelines for Committing Lab VIEW FPGA Compile Results
160(1)
4.9 Debugging on Hardware
160(2)
4.9.1 Streaming
160(1)
4.9.2 Counters and Latches
161(1)
4.9.3 Interactive Front Panel Communication
161(1)
4.10 Export Options
162(1)
4.10.1 Vivado Export
162(1)
4.10.2 Lab VIEW FPGA IP Export
162(1)
4.11 Summary
163(6)
References
164(5)
Chapter 5 RF Lab VIEW FPGA Case Studies
169(48)
5.1 Overview
169(1)
5.2 Problem Definition
170(1)
5.3 NI Platform
171(4)
5.3.1 Market Overview
175(1)
5.4 Common NI FPGA Architectures
175(3)
5.4.1 Summary
177(1)
5.5 Components of an RF Test System
178(15)
5.5.1 Front End
179(4)
5.5.2 FPGA DSP
183(9)
5.5.3 CPU/GPU DSP
192(1)
5.5.4 Storage
192(1)
5.6 Case Studies
193(24)
5.6.1 NIVST
193(10)
5.6.2 RTSA
203(6)
5.6.3 Multichannel Phased Array Systems
209(4)
5.6.4 Other Case Studies
213(1)
References
213(4)
Chapter 6 Looking Ahead
217(20)
6.1 FPGA Overlays
217(3)
6.1.1 NI VST as an FPGA Overlay
218(1)
6.1.2 Xilinx PYNQ
219(1)
6.2 SoC Architectures
220(1)
6.3 FPGA Platforms
221(1)
6.3.1 Lab VIEW NXG
222(1)
6.4 RISC-V
222(1)
6.5 Echolocation in Nature
223(1)
6.6 How to Stay Current
223(3)
6.6.1 Publications and Online Resources
225(1)
6.6.2 Recommended Conferences
226(1)
6.7 Conclusions
226(3)
References
226(3)
Selected Bibliography
229(1)
National Instruments References
229(3)
Lab VIEW High Performance FPGA Developer's Guide
229(1)
Compact RIO Developer's Guide
230(1)
NI High-Speed Serial Instruments User Manual
230(1)
NI-7931R, 7932R, and 7935R User Manual
230(1)
Other Lab VIEW FPGA Content on the NI's Website
230(1)
NI Center of Excellence
230(1)
NI Training
231(1)
Books
232(2)
Lab VIEW FPGA Books
232(1)
Lab VIEW Books
232(1)
RF, EW, and Radar Books
232(1)
FPGA Books
233(1)
Management Books
233(1)
Online Videos
234(1)
Organizations and Periodicals
235(1)
Online RF, Radar, and EW Resources
235(1)
Vendor Resources
236(1)
Summary
236(1)
About the Author 237(2)
Index 239