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Introduction to Logic Circuits & Logic Design with Verilog 1st ed. 2017 [Kõva köide]

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  • Formaat: Hardback, 459 pages, kõrgus x laius: 254x178 mm, 426 Illustrations, color; 50 Illustrations, black and white; XVI, 459 p. 476 illus., 426 illus. in color., 1 Hardback
  • Ilmumisaeg: 25-Apr-2017
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319538829
  • ISBN-13: 9783319538822
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Introduction to Logic Circuits & Logic Design with Verilog 1st ed. 2017Suurem pilt
  • Formaat: Hardback, 459 pages, kõrgus x laius: 254x178 mm, 426 Illustrations, color; 50 Illustrations, black and white; XVI, 459 p. 476 illus., 426 illus. in color., 1 Hardback
  • Ilmumisaeg: 25-Apr-2017
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319538829
  • ISBN-13: 9783319538822
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783319538822.html
Märksõnad:
This textbook for courses in Digital Systems Design introduces students to the fundamental hardware used in modern computers. Coverage includes both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). Using this textbook enables readers to design digital systems using the modern HDL approach, but they have a broad foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning Goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on each outcome.

Arvustused

This book presents the logical components, step by step, to develop a complete computer system. Thus, it presents a comprehensive view of a computer system that can be developed from logical circuits; combinational and sequential circuits are not explored in detail. The book is suitable for undergraduates; students will learn both the logic and experimental aspects of a computer component using Verilog. (J. Arul, Computing Reviews, July, 2018)

1 Introduction: Analog VS. Digital
1(6)
1.1 Differences Between Analog and Digital Systems
1(1)
1.2 Advantages of Digital Systems over Analog Systems
2(5)
2 Number Systems
7(30)
2.1 Positional Number Systems
7(3)
2.1.1 Generic Structure
8(1)
2.1.2 Decimal Number System (Base 10)
9(1)
2.1.3 Binary Number System (Base 2)
9(1)
2.14 Octal Number System (Base 8)
10(1)
2.1.5 Hexadecimal Number System (Base 16)
10(1)
2.2 Base Conversion
11(10)
2.2.7 Converting to Decimal
11(3)
2.2.2 Converting From Decimal
14(3)
2.2.3 Converting Between 2n Bases
17(4)
2.3 Binary Arithmetic
21(2)
2.3.1 Addition (Carries)
21(1)
2.3.2 Subtraction (Borrows)
22(1)
2.4 Unsigned and Signed Numbers
23(14)
2.4.1 Unsigned Numbers
24(1)
2.4.2 Signed Numbers
24(13)
3 Digital Circuitry And Interfacing
37(44)
3.1 Basic Gates
37(2)
3.1.1 Describing the Operation of a Logic Circuit
37(2)
3.12 The Buffer
39(1)
3.13 The Inverter
40(1)
3.14 The AND Gate
40(1)
3.1.5 The NAND Gate
41(1)
3.16 The OR Gate
41(1)
3.17 The NOR Gate
41(1)
3.18 The XOR Gate
42(1)
3.19 The XNOR Gate
43(1)
3.2 Digital Circuit Operation
44(12)
3.2.1 Logic Levels
44(1)
3.2.2 Output DC Specifications
45(1)
3.2.3 Input DC Specifications
46(1)
3.2.4 Noise Margins
47(1)
3.2.5 Power Supplies
48(3)
3.2.6 Switching Characteristics
51(1)
3.2.7 Datasheets
51(5)
3.3 Logic Families
56(15)
3.3.1 Complementary Metal Oxide Semiconductors (CMOS)
56(9)
3.3.2 Transistor-Transistor Logic (TTL)
65(2)
3.3.3 The 7400 Series Logic Families
67(4)
3.4 Driving Loads
71(10)
3.4.1 Driving Other Gates
71(2)
3.4.2 Driving Resistive Loads
73(2)
3.4.3 Driving LEDs
75(6)
4 Combinational Logic Design
81(60)
4.1 Boolean Algebra
81(18)
4.1.1 Operations
82(1)
4.1.2 Axioms
82(1)
4.1.3 Theorems
83(15)
4.1.4 Functionally Complete Operation Sets
98(1)
4.2 Combinational Logic Analysis
99(4)
4.2.1 Finding the Logic Expression from a Logic Diagram
99(1)
4.2.2 Finding the Truth Table from a Logic Diagram
100(1)
4.2.3 Timing Analysis of a Combinational Logic Circuit
101(2)
4.3 Combinational Logic Synthesis
103(9)
4.3.1 Canonical Sum of Products
103(1)
4.3.2 The Minterm List (Σ)
104(2)
4.3.3 Canonical Product of Sums (POS)
106(2)
4.3.4 The Maxterm List (II)
108(2)
4.3.5 Minterm and Maxterm List Equivalence
110(2)
4.4 Logic Minimization
112(17)
4.4.1 Algebraic Minimization
112(1)
4.4.2 Minimization Using Karnaugh Maps
113(12)
4.4.3 Don't Cares
125(1)
4.4.4 Using XOR Gates
126(3)
4.5 Timing Hazards & Glitches
129(12)
5 VERILOG (PART 1)
141(40)
5.1 History of Hardware Description Languages
142(3)
5.2 HDL Abstraction
145(4)
5.3 The Modern Digital Design Flow
149(3)
5.4 Verilog Constructs
152(12)
5.4.1 Data Types
153(3)
5.4.2 The Module
156(3)
5.4.3 Verilog Operators
159(5)
5.5 Modeling Concurrent Functionality in Verilog
164(6)
5.5.1 Continuous Assignment
164(1)
5.5.2 Continuous Assignment with Logical Operators
164(1)
5.5.3 Continuous Assignment with Conditional Operators
165(2)
5.5.4 Continuous Assignment with Delay
167(3)
5.6 Structural Design and Hierarchy
170(5)
5.6.1 Lower-Level Module Instantiation
170(2)
5.6.2 Gate Level Primitives
172(1)
5.6.3 User-Defined Primitives
173(1)
5.6.4 Adding Delay to Primitives
174(1)
5.7 Overview of Simulation Test Benches
175(6)
6 MSI Logic
181(18)
6.1 Decoders
181(7)
6.1.1 Example: One-Hot Decoder
181(3)
6.1.2 Example: 7-Segment Display Decoder
184(4)
6.2 Encoders
188(2)
6.2.1 Example: One-Hot Binary Encoder
188(2)
6.3 Multiplexers
190(3)
6.4 Demultiplexers
193(6)
7 Sequential Logic Design
199(72)
7.1 Sequential Logic Storage Devices
199(15)
7.1.1 The Cross-Coupled Inverter Pair
199(1)
7.1.2 Metastability
200(2)
7.1.3 The SR Latch
202(3)
7.1.4 The S'R' Latch
205(3)
7.1.5 SR Latch with Enable
208(1)
7.1.6 The D-Latch
209(2)
7.1.7 The D-Flip-Flop
211(3)
7.2 Sequential Logic Timing Considerations
214(2)
7.3 Common Circuits Based on Sequential Storage Devices
216(7)
7.3.1 Toggle Flop Clock Divider
216(1)
7.3.2 Ripple Counter
217(1)
7.3.3 Switch Debouncing
217(4)
7.3.4 Shift Registers
221(2)
7.4 Finite State Machines
223(18)
7.4.1 Describing the Functionality of a FSM
223(2)
7.4.2 Logic Synthesis for a FSM
225(7)
7.4.3 FSM Design Process Overview
232(1)
7.4.4 FSM Design Examples
233(8)
7.5 Counters
241(13)
7.5.1 2-Bit Binary Up Counter
241(1)
7.5.2 2-Bit Binary Up/Down Counter
242(3)
7.5.3 2-Bit Gray Code Up Counter
245(2)
7.5.4 2-Bit Gray Code Up/Down Counter
247(2)
7.5.5 3-Bit One-Hot Up Counter
249(1)
7.5.6 3-Bit One-Hot Up/Down Counter
250(4)
7.6 Finite State Machine's Reset Condition
254(1)
7.7 Sequential Logic Analysis
255(16)
7.7.1 Finding the State Equations and Output Logic Expressions of a FSM
255(1)
7.7.2 Finding the State Transition Table of a FSM
256(1)
7.7.3 Finding the State Diagram of a FSM
257(1)
7.7.4 Determining the Maximum Clock Frequency of a FSM
258(13)
8 Verilog (PART 2)
271(32)
8.1 Procedural Assignment
271(8)
8.1.1 Procedural Blocks
271(3)
8.1.2 Procedural Statements
274(5)
8.13 Statement Groups
279(1)
8.14 Local Variables
279(1)
8.2 Conditional Programming Constructs
280(6)
8.2.1 if-else Statements
280(1)
8.2.2 case Statements
281(2)
8.2.3 casez and casex Statements
283(1)
8.2.4 forever Loops
283(1)
8.2.5 while Loops
283(1)
8.2.6 repeat Loops
284(1)
8.2.7 for Loops v
284(1)
8.2.8 disable
285(1)
8.3 System Tasks
286(4)
8.3.1 Text Output
286(1)
8.3.2 File Input/Output
287(2)
8.3.3 Simulation Control and Monitoring
289(1)
8.4 Test Benches
290(13)
8.4.1 Common Stimulus Generation Techniques
291(1)
8.4.2 Printing Results to the Simulator Transcript
292(1)
8.4.3 Automatic Result Checking
293(2)
8.4.4 Using Loops to Generate Stimulus
295(1)
8.4.5 Using External Files in Test Benches
296(7)
9 Behavioral Modeling Of Sequential Logic
303(28)
9.1 Modeling Sequential Storage Devices in Verilog
303(1)
9.1.1 D-Latch
303(1)
9.12 D-Flip-Flop
304(2)
9.1.3 D-Flip-Flop with Asynchronous Reset
304(1)
9.1.4 D-Flip-Flop with Asynchronous Reset and Preset
305(1)
9.15 D-Flip-Flop with Synchronous Enable
306(1)
9.2 Modeling Finite State Machines in Verilog
307(6)
9.2.1 Modeling the States
309(1)
9.2.2 The State Memory Block
309(1)
9.2.3 The Next State Logic Block
309(1)
9.2.4 The Output Logic Block
310(2)
9.2.5 Changing the State Encoding Approach
312(1)
9.3 FSM Design Examples in Verilog
313(6)
9.3.1 Serial Bit Sequence Detector in Verilog
313(2)
9.3.2 Vending Machine Controller in Verilog
315(2)
9.3.3 2-Bit, Binary Up/Down Counter in Verilog
317(2)
9.4 Modeling Counters in Verilog
319(3)
9.4.1 Counters in Verilog Using a Single Procedural Block
319(1)
9.4.2 Counters with Range Checking
320(1)
9.4.3 Counters with Enables in Verilog
320(1)
9.4.4 Counters with Loads
321(1)
9.5 RTL Modeling
322(9)
9.5.1 Modeling Registers in Verilog
322(1)
9.5.2 Registers as Agents on a Data Bus
323(2)
9.5.3 Shift Registers in Verilog
325(6)
10 Memory
331(28)
10.1 Memory Architecture and Terminology
331(2)
10.1.1 Memory Map Model
331(1)
10.1.2 Volatile Versus Non-volatile Memory
332(1)
10.1.3 Read Only Versus Read Write Memory
332(1)
10.1.4 Random Access Versus Sequential Access
332(1)
10.2 Non-volatile Memory Technology
333(9)
10.2.1 ROM Architecture
333(3)
10.2.2 Mask Read Only Memory (MROM)
336(1)
10.2.3 Programmable Read Only Memory (PROM)
337(1)
10.2.4 Erasable Programmable Read Only Memory (EPROM)
338(2)
10.2.5 Electrically Erasable Programmable Read Only Memory (EEPROM)
340(1)
10.2.6 FLASH Memory
341(1)
10.3 Volatile Memory Technology
342(10)
10.3.1 Static Random Access Memory (SRAM)
342(3)
10.3.2 Dynamic Random Access Memory (DRAM)
345(7)
10.4 Modeling Memory with Verilog
352(7)
10.4.1 Read-Only Memory in Verilog
352(1)
10.4.2 Read/Write Memory in Verilog
353(6)
11 Programmable Logic
359(14)
11.1 Programmable Arrays
359(4)
11.1.1 Programmable Logic Array (PLA)
359(1)
11.1.2 Programmable Array Logic (PAL)
360(1)
11.1.3 Generic Array Logic (GAL)
361(1)
11.1.4 Hard Array Logic (HAL)
362(1)
11.1.5 Complex Programmable Logic Devices (CPLD)
362(1)
11.2 Field Programmable Gate Arrays (FPGAs)
363(10)
11.2.1 Configurable Logic Block (or Logic Element)
364(1)
11.2.2 Look-Up Tables (LUTs)
365(3)
11.2.3 Programmable Interconnect Points (PIPs)
368(1)
11.2.4 Input/Output Block (IOBs)
369(1)
11.2.5 Configuration Memory
370(3)
12 Arithmetic Circuits
373(30)
12.1 Addition
373(13)
12.1.1 Half Adders
373(1)
12.1.2 Full Adders
374(2)
12.1.3 Ripple Carry Adder (RCA)
376(2)
12.1.4 Carry Look Ahead Adder (CLA)
378(3)
12.1.5 Adders in Verilog
381(5)
12.2 Subtraction
386(3)
12.3 Multiplication
389(6)
12.3.1 Unsigned Multiplication
389(3)
12.3.2 A Simple Circuit to Multiply by Powers of Two
392(1)
12.3.3 Signed Multiplication
393(2)
12.4 Division
395(8)
12.4.1 Unsigned Division
395(3)
12.4.2 A Simple Circuit to Divide by Powers of Two
398(1)
12.4.3 Signed Division
399(4)
13 Computer System Design
403(46)
13.1 Computer Hardware
403(5)
13.1.1 Program Memory
404(1)
13.1.2 Data Memory
404(1)
13.1.3 Input/Output Ports
404(1)
13.1.4 Central Processing Unit
405(1)
13.1.5 A Memory Mapped System
406(2)
13.2 Computer Software
408(9)
13.2.1 Opcodes and Operands
409(1)
13.2.2 Addressing Modes
409(1)
13.2.3 Classes of Instructions
410(7)
13.3 Computer Implementation - An 8-Bit Computer Example
417(27)
13.3.1 Top Level Block Diagram
417(1)
13.3.2 Instruction Set Design
418(1)
13.3.3 Memory System Implementation
419(4)
13.3.4 CPU Implementation
423(21)
13.4 Architecture Considerations
444(5)
13.4.1 Von Neumann Architecture
444(1)
13.4.2 Harvard Architecture
444(5)
Appendix A List Of Worked Examples 449(6)
Index 455
Brock LaMeres joined the Montana State ECE faculty in July of 2006. He received his Ph.D. in electrical engineering from the University of Colorado, Boulder in December of 2005, his MSEE from the University of Colorado, Colorado Springs in May of 2001, and his BSEE from Montana State University, Bozeman in December of 1998. LaMeres teaches and conducts research in the area of digital systems with particular emphasis on exploiting reprogrammable fabrics to deliver more effective computer systems. LaMeres is also studying how engineering education can be improved using innovative e-learning environments.

LaMeres has published over 70 manuscripts and 3 textbooks in the area of high speed digital systems. LaMeres has also been granted 13 US patents in the area of digital signal propagation. LaMeres is a Senior Member of IEEE and a Registered Professional Engineer in the States of Montana and Colorado. Dr. LaMeres is a member of AESS, ASEE and serves as the faculty advisor of thestudent branch of IEEE at MSU.







Prior to coming to MSU, Dr. LaMeres worked as an R&D engineer for Agilent Technologies in Colorado Springs, CO from 1999 to 2006. LaMeres was a hardware design engineer in the Logic Analysis R&D lab. He designed acquisition hardware for the 16910/11/12 and 16950 Logic Analyzer systems in addition to developing a variety of probing solutions.