Muutke küpsiste eelistusi

Introduction to Microelectronics to Nanoelectronics: Design and Technology [Kõva köide]

(IIIT, Naya Raipur, Chhattisgarh, India), (IIIT, Naya Raipur, Chhattisgarh, India), , (IIIT, Chhattisgarh, India)
  • Formaat: Hardback, 328 pages, kõrgus x laius: 234x156 mm, kaal: 662 g, 46 Tables, black and white; 243 Illustrations, black and white
  • Ilmumisaeg: 25-Nov-2020
  • Kirjastus: CRC Press
  • ISBN-10: 0367502372
  • ISBN-13: 9780367502379
Teised raamatud teemal:
Introduction to Microelectronics to Nanoelectronics: Design and TechnologySuurem pilt
  • Formaat: Hardback, 328 pages, kõrgus x laius: 234x156 mm, kaal: 662 g, 46 Tables, black and white; 243 Illustrations, black and white
  • Ilmumisaeg: 25-Nov-2020
  • Kirjastus: CRC Press
  • ISBN-10: 0367502372
  • ISBN-13: 9780367502379
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780367502379.html
Märksõnad:
Focussing on micro- and nanoelectronics design and technology, this book provides thorough analysis and demonstration, starting from semiconductor devices to VLSI fabrication, designing (analog and digital), on-chip interconnect modeling culminating with emerging non-silicon/ nano devices. It gives detailed description of both theoretical as well as industry standard HSPICE, Verilog, Cadence simulation based real-time modeling approach with focus on fabrication of bulk and nano-devices. Each chapter of this proposed title starts with a brief introduction of the presented topic and ends with a summary indicating the futuristic aspect including practice questions. Aimed at researchers and senior undergraduate/graduate students in electrical and electronics engineering, microelectronics, nanoelectronics and nanotechnology, this book:











Provides broad and comprehensive coverage from Microelectronics to Nanoelectronics including design in analog and digital electronics.





Includes HDL, and VLSI design going into the nanoelectronics arena.





Discusses devices, circuit analysis, design methodology, and real-time simulation based on industry standard HSPICE tool.





Explores emerging devices such as FinFETs, Tunnel FETs (TFETs) and CNTFETs including their circuit co-designing. Covers real time illustration using industry standard Verilog, Cadence and Synopsys simulations.
List of Figures xvii
List of Tables xxix
List of Abbreviations xxxiii
Preface xxxvii
Authors xli
Acknowledgments xliii
Chapter 1 Semiconductor Physics and Devices 1(36)
1.1 Introduction
1(7)
1.1.1 Conduction in Solids
1(1)
1.1.2 Conductors, Insulators, and Semiconductors
2(1)
1.1.2.1 Conductors
2(1)
1.1.2.2 Insulators
3(1)
1.1.2.3 Semiconductors
3(1)
1.1.3 P-Type and N-Type Semiconductors
3(4)
1.1.3.1 N-Type Semiconductors
5(1)
1.1.3.2 P-Type Semiconductors
6(1)
1.1.4 Semiconductor Conductivity
7(1)
1.2 Diode
8(10)
1.2.1 Diode Structure and Characteristics
8(1)
1.2.2 PN Diode Structure
8(2)
1.2.2.1 Forward and Reverse Bias Regions
10(1)
1.2.3 Zener Diode Structure
10(1)
1.2.4 Diode Applications
11(7)
1.2.4.1 Rectifiers
11(3)
1.2.4.2 Diode Logic Gates
14(1)
1.2.4.3 Clipping and Clamping Circuits
15(3)
1.3 Bipolar Junction Transistor
18(5)
1.3.1 Symbol and Physical Structure
18(2)
1.3.1.1 Operation and Several Current Components
19(1)
1.3.2 BJT Configurations
20(2)
1.3.2.1 Common Base (CB) Configuration
21(1)
1.3.2.2 Common Emitter (CE) Configuration
21(1)
1.3.2.3 Common Collector (CC) Configuration
21(1)
1.3.2.4 BJT in CE Configuration: Operation and I-V Characteristic
21(1)
1.3.3 Second-Order Effects
22(1)
1.3.3.1 Base-Width Modulation
23(1)
1.3.3.2 Recombination in the Depletion Region
23(1)
1.3.3.3 Breakdown Mechanism in BJT
23(1)
1.4 Field-Effect Transistor
23(6)
1.4.1 Junction Field-Effect Transistor (JFET)
23(3)
1.4.1.1 Symbol and Physical Structure
24(1)
1.4.1.2 Operation of JFET
24(1)
1.4.1.3 Current-Voltage Characteristics and Regions of Operation
25(1)
1.4.2 Metal-Oxide-Semiconductor Field-Effect Transistor
26(3)
1.4.2.1 Symbol and Device Structure
26(1)
1.4.2.2 Device Operation
27(2)
1.4.3 Advantages of MOSFET Over JFET
29(1)
1.5 Emerging Devices Beyond CMOS
29(3)
1.5.1 Issues with CMOS Technology Scaling
30(1)
1.5.1.1 Velocity Saturation and Mobility Degradation
30(1)
1.5.1.2 Tunneling Current Through Gate Insulator
30(1)
1.5.1.3 High Field Effects
30(1)
1.5.1.4 Power Limitation
30(1)
1.5.1.5 Material Limitation
30(1)
1.5.2 Emerging Nanoscale Device Technologies
31(6)
1.5.2.1 Gate-All-Around (GAA) Nanowire (NW) MOSFET
31(1)
1.5.2.2 Fin Field-Effect Transistor (FinFET)
31(1)
1.5.2.3 Carbon Nanotube FETs (CNTFETs)
31(1)
1.5.2.4 Tunnel FET (TFET)
31(1)
1.6 Summary
32(1)
1.7 Multiple-Choice Questions
33(1)
1.8 Small Answer Questions
34(1)
1.9 Long Answer Questions
35(1)
References
35(2)
Chapter 2 VLSI Scaling and Fabrication 37(46)
2.1 Introduction to VLSI Scaling
37(4)
2.1.1 History and Introduction of VLSI Technology
37(1)
2.1.2 VLSI Design Concept
38(1)
2.1.3 Moore's Law
39(1)
2.1.4 Scale of Integration
40(1)
2.1.5 Types of VLSI Chips (Analog and Digital)
40(1)
2.1.6 Layout, Micron, and Lambda Rules
40(1)
2.2 VLSI Fabrication Process
41(30)
2.2.1 Purification, Crystal Growth, and Wafer Processing (CZ and FZ Process)
41(5)
2.2.1.1 Introduction
41(1)
2.2.1.2 Electronic Grade Silicon
42(1)
2.2.1.3 Czochralski Crystal Growing
43(3)
2.2.1.4 Silicon Shaping
46(1)
2.2.2 Oxidation
46(3)
2.2.2.1 Introduction
46(1)
2.2.2.2 Growth Mechanism
47(1)
2.2.2.3 Oxidation Techniques and Systems
47(1)
2.2.2.4 Redistribution of Dopants at Interface
48(1)
2.2.2.5 Oxidation of Polysilicon
48(1)
2.2.3 Epitaxial Deposition
49(3)
2.2.3.1 Introduction
49(1)
2.2.3.2 Vapor-Phase Epitaxy
50(1)
2.2.3.3 Molecular Beam Epitaxy
51(1)
2.2.3.4 Silicon on Insulator
51(1)
2.2.4 Lithography
52(5)
2.2.4.1 Introduction
53(1)
2.2.4.2 Optical Lithography
53(1)
2.2.4.3 Electron Beam Lithography
54(2)
2.2.4.4 X-ray Lithography
56(1)
2.2.5 Polysilicon and Dielectric Deposition
57(3)
2.2.5.1 Deposition Process
57(2)
2.2.5.2 Polysilicon
59(1)
2.2.5.3 Silicon Dioxide
59(1)
2.2.5.4 Silicon Nitride
60(1)
2.2.6 Diffusion
60(2)
2.2.6.1 Introduction and Model of Diffusion
60(1)
2.2.6.2 Flick's First Law of Diffusion
61(1)
2.2.6.3 Diffusion Factors
61(1)
2.2.6.4 Diffusivity in Polycrystalline Silicon and SiO2
62(1)
2.2.7 Ion Implantation
62(3)
2.2.7.1 Introduction
63(1)
2.2.7.2 Range Theory
63(1)
2.2.7.3 Implantation Equipment
64(1)
2.2.7.4 Annealing
65(1)
2.2.8 Metallization
65(4)
2.2.8.1 Choice of Metal
65(2)
2.2.8.2 Metallization Process
67(1)
2.2.8.3 Metallization Problem
67(1)
2.2.8.4 New Approaches Toward Metallization
68(1)
2.2.9 Etching Process
69(2)
2.2.9.1 Dry or Plasma Etching
69(1)
2.2.9.2 Wet Etching
70(1)
2.3 Basic CMOS Technology
71(4)
2.3.1 N-Well and P-Well CMOS Process
71(3)
2.3.2 Twin-Tub Process
74(1)
2.4 Summary
75(1)
2.5 Multiple-Choice Questions
75(3)
2.6 Short Answer Questions
78(1)
2.7 Long Answer Questions
78(1)
References
79(4)
Chapter 3 MOSFET Modeling 83(36)
3.1 Introduction to MOS Transistor
83(10)
3.1.1 Characteristics of MOS Transistor
84(5)
3.1.2 Hot Carrier Effects
89(1)
3.1.3 Parasitics of MOSFET
89(3)
3.1.4 MOSFET Circuit Models
92(1)
3.2 MOS Capacitor
93(4)
3.2.1 MOS Capacitor with Zero and Nonzero Bias
93(3)
3.2.2 Capacitance-Voltage Curves
96(1)
3.2.3 Anomalous Capacitance-Voltage Curves
97(1)
3.3 MOSFET DC and Dynamic Models
97(5)
3.3.1 Pao-Sah Model
97(1)
3.3.2 Charge Sheet Model
97(1)
3.3.3 Piece-Wise Model for Enhancement Devices
98(1)
3.3.4 Small Geometry Model
99(1)
3.3.5 Intrinsic Charges and Capacitance
100(1)
3.3.6 Meyer Model
101(1)
3.4 MOSFET Modeling Using SPICE
102(11)
3.4.1 Basic Concepts of Modeling
102(1)
3.4.2 Model Equations
102(6)
3.4.2.1 Level 1 Model Equation
102(3)
3.4.2.2 Level 2 Model Equation
105(1)
3.4.2.3 Level 3 Model Equation
105(2)
3.4.2.4 BSIM Model
107(1)
3.4.3 Examples Using HSPICE
108(5)
3.5 Summary
113(1)
3.6 Multiple-Choice Questions
113(2)
3.7 Short Answer Questions
115(1)
3.8 Long Answer Questions
115(1)
References
115(4)
Chapter 4 Combinational and Sequential Design in CMOS 119(28)
4.1 CMOS Inverter
119(2)
4.1.1 Design
119(1)
4.1.2 Operation
119(1)
4.1.3 Transient and VTC Characteristics
120(1)
4.1.4 Significance of the CMOS Inverter
120(1)
4.2 Static Behavior of the Inverter
121(2)
4.2.1 Switching Threshold
121(1)
4.2.2 Noise Margin
122(1)
4.2.3 Robustness of the CMOS Inverter By Scaling Supply Voltage
122(1)
4.3 Dynamic Behavior of CMOS Inverter
123(6)
4.3.1 Capacitances
124(2)
4.3.1.1 Gate-Drain Capacitance
124(1)
4.3.1.2 Diffusion Capacitance (Cdb1, Cdb2)
124(1)
4.3.1.3 Gate Capacitance (Cg3, Cg4)
125(1)
4.3.1.4 Propagation Delay of the CMOS Inverter
125(1)
4.3.2 Power and Energy Consumption
126(3)
4.3.2.1 Power Consumption
126(1)
4.3.2.2 Dynamic Power Consumption
126(1)
4.3.2.3 Static Power Consumption
127(1)
4.3.2.4 Direct Path Power Consumption
128(1)
4.3.2.5 Total Power Consumption
128(1)
4.4 Design of Combinational Logic Design
129(9)
4.4.1 Complementary CMOS Logic
129(3)
4.4.1.1 Guidelines in Designing Static CMOS Logic
130(1)
4.4.1.2 Two- and Multi-Input Static Complementary Gates
130(2)
4.4.1.3 Sizing Static Complementary Gates for optimum Propagation Delay
132(1)
4.4.2 Ratioed Logic
132(2)
4.4.2.1 Differential Cascade Voltage Switch Logic (DCVSL)
134(1)
4.4.3 Pass-Transistor Logic
134(4)
4.4.3.1 Differential Pass Transistor Logic
136(1)
4.4.3.2 Transmission Gate Logic
137(1)
4.5 CMOS Sequential Design
138(2)
4.5.1 Introduction
139(1)
4.5.2 Metrics for CMOS Sequential Design
139(1)
4.6 Static Latches and Registers
140(2)
4.6.1 The Bistability Principle
140(1)
4.6.2 SR Flip-Flops
141(1)
4.6.3 D-latches and Flip-Flops
141(1)
4.6.4 Master-Slave Flip-Flop
142(1)
4.7 Summary
142(1)
4.8 Multiple-Choice Questions
143(1)
4.9 Short-Answer Questions
144(1)
4.10 Long-Answer Questions
144(2)
References
146(1)
Chapter 5 Analog Circuit Design 147(22)
5.1 Introduction to Analog Design
147(1)
5.2 MOS Device from Analog Perspective
147(4)
5.2.1 I/V Characteristics
147(2)
5.2.2 Second-Order Effects
149(1)
5.2.2.1 Body Effect
149(1)
5.2.2.2 Channel-Length Modulation
150(1)
5.2.2.3 Subthreshold Conduction
150(1)
5.2.3 MOS Small Signal Model
150(1)
5.3 Single-Stage Amplifier
151(3)
5.3.1 Common Source
151(1)
5.3.2 Common Gate
152(1)
5.3.3 Source Follower
153(1)
5.4 Current Mirrors
154(3)
5.4.1 Introduction
154(1)
5.4.2 Basic Current Mirror
155(1)
5.4.3 Cascode Current Mirror
156(1)
5.5 Differential Amplifiers
157(2)
5.5.1 Single-Ended and Differential Operation
157(1)
5.5.2 Basic Differential Pair
157(1)
5.5.2.1 Input-Output Characteristics
157(1)
5.5.3 Differential Pair With MOS Load
158(1)
5.6 Operational Amplifier
159(2)
5.6.1 Fundamentals and General Op-amp Metrics
159(1)
5.6.2 Two-Stage Op-amp
160(1)
5.7 Digital-to-Analog and Analog-to-Digital Converters
161(4)
5.7.1 Introduction
161(1)
5.7.1.1 DAC: Digital-to-Analog Converter
161(1)
5.7.1.2 ADC: Analog to Digital Converter
161(1)
5.7.2 Types of Digital-to-Analog Converters
161(2)
5.7.2.1 Weighted Resistor DAC
161(1)
5.7.2.2 Weighted Capacitor DAC
162(1)
5.7.3 Types of Analog-to-Digital Converters
163(6)
5.7.3.1 Flash Converters
163(1)
5.7.3.2 Successive-Approximation ADC (SA ADC)
164(1)
5.8 Summary
165(1)
5.9 Multiple-Choice Questions
166(1)
5.10 Short Answer Questions
167(1)
5.11 Long Answer Questions
167(1)
References
168(1)
Chapter 6 Digital Design Through Verilog HDL 169(26)
6.1 Introduction
169(4)
6.1.1 What Is Verilog HDL?
169(1)
6.1.2 Background
169(1)
6.1.3 Compiler Directives
169(1)
6.1.4 Data Types
170(1)
6.1.5 Operators
171(2)
6.1.5.1 Arithmetic Operator
171(1)
6.1.5.2 Equality Operators
171(1)
6.1.5.3 Relational Operators
171(1)
6.1.5.4 Logical Operators
172(1)
6.1.5.5 Bitwise Operators
172(1)
6.1.5.6 Conditional Operator
172(1)
6.1.5.7 Concatenation Operator
173(1)
6.2 Module and Test Bench Definitions
173(2)
6.2.1 Module
173(1)
6.2.2 Test Bench
174(1)
6.3 Gate-Level Modeling
175(5)
6.3.1 Built-In Primitives
176(1)
6.3.2 Single and Multiple Input Gates
176(1)
6.3.3 Tristate Gates
177(1)
6.3.4 MOS Switches
178(1)
6.3.5 Gate Delays
179(1)
6.3.6 Example
180(1)
6.4 Dataflow Modelling
180(2)
6.4.1 Continuous Assignment
181(1)
6.4.2 Delays
181(1)
6.4.3 Examples: A Verilog Program for Full Adder
182(1)
6.5 Behavioral Modeling
182(8)
6.5.1 Initial Statement
182(1)
6.5.2 Always Statement
183(1)
6.5.3 Procedural Assignments
184(1)
6.5.3.1 Blocking Procedural Assignment
184(1)
6.5.3.2 Nonblocking Procedural Assignment
185(1)
6.5.4 Conditional Statements
185(2)
6.5.5 Loop Statements
187(2)
6.5.5.1 For-Loop Statement
188(1)
6.5.5.2 While-Loop Statement
188(1)
6.5.5.3 Forever-Loop Statement
189(1)
6.5.6 Examples
189(1)
6.6 Tasks and Functions
190(2)
6.6.1 Task
190(1)
6.6.2 Function
191(1)
6.7 Summary
192(1)
6.8 Multiple-Choice Questions
192(2)
6.9 Short Answer Questions
194(1)
6.10 Long Answer Questions
194(1)
References
194(1)
Chapter 7 VLSI Interconnect and Implementation 195(42)
7.1 An Overview of the VLSI Interconnect Problem
195(3)
7.1.1 Interconnect Scaling Problem
195(1)
7.1.2 Implementation of Interconnect Problem
196(2)
7.2 Interconnect Aware Design Methodology and Electrical Modeling
198(6)
7.2.1 Impact of Scaling
198(1)
7.2.2 Transistor Scaling
198(6)
7.2.3 Interconnect Scaling
204(1)
7.3 Electrical Circuit Model of Interconnect
204(7)
7.3.1 Ideal Interconnect
205(1)
7.3.2 Resistive Interconnect
205(2)
7.3.3 Capacitive Interconnect
207(2)
7.3.4 Resistive Interconnect Tree
209(2)
7.4 Estimation of Interconnect Parasitics
211(7)
7.4.1 Interconnect Resistance Estimation
211(2)
7.4.2 Interconnect Inductance Estimation
213(2)
7.4.3 Interconnect Capacitance Estimation
215(3)
7.4.3.1 Parallel Plate Capacitor
216(1)
7.4.3.2 Fringing Capacitance
216(1)
7.4.3.3 Lateral Capacitance
216(2)
7.5 Calculation of Interconnect Delay
218(9)
7.5.1 RC Delay Model
219(3)
7.5.2 Elmore Delay Model
222(1)
7.5.3 Transfer Function Model Based on ABCD Parameter Matrix
223(1)
7.5.4 Finite Difference Time Domain Model
224(3)
7.6 Estimation of Interconnect Crosstalk Noise
227(1)
7.7 Estimation of Interconnect Power Dissipation
228(3)
7.8 Summary
231(1)
7.9 Multiple-Choice Questions
231(3)
7.10 Short Answer Questions
234(1)
7.11 Long Answer Questions
234(1)
References
234(3)
Chapter 8 VLSI Design and Testability 237(14)
8.1 Preamble
237(1)
8.2 Basic Digital Troubleshoot
237(2)
8.2.1 Manufacturing Test
237(1)
8.2.2 Tester and Test Fixtures
238(1)
8.2.3 Test Programs
238(1)
8.3 Effect of Physical Faults on Circuit Behavior
239(1)
8.3.1 Fault Models
239(1)
8.3.1.1 Line Stuck-at Faults
239(1)
8.3.1.2 Transistor Stuck-at Faults
239(1)
8.3.1.3 Floating Line Faults
239(1)
8.3.1.4 Bridging Faults
240(1)
8.4 Test Principles of Manufacturing
240(2)
8.4.1 Observability
240(1)
8.4.2 Controllability
240(1)
8.4.3 Fault Coverage
241(1)
8.4.4 Automatic Test Pattern Generation (ATPG)
241(1)
8.4.5 Delay Fault Testing
242(1)
8.5 Test Approaches
242(2)
8.5.1 Ad Hoc DFT Techniques
242(1)
8.5.2 Scan Design Test
243(1)
8.5.3 Built-in Self-Test (BIST)
244(1)
8.5.4 IDDQ Testing
244(1)
8.6 Design for Manufacturability (DFM)
244(1)
8.7 System On Chip (SOC) Testing
245(1)
8.8 Summary
246(1)
8.9 Multiple-Choice Questions
246(2)
8.10 Short Answer Questions
248(1)
8.11 Long Answer Questions
249(1)
References
249(2)
Chapter 9 Nanomaterials and Applications 251(44)
9.1 Preamble of Nanomaterials
251(1)
9.2 Introduction to Carbon Nanotubes
251(5)
9.2.1 The Concept of Chirality on CNT
252(1)
9.2.2 Electronic Band Structure
253(2)
9.2.3 Brillouin Zone
255(1)
9.3 Overview of Graphene Nanoribbon
256(2)
9.4 Properties of CNT and GNR
258(1)
9.5 Fabrication Approaches for Graphene Nanostructure
258(3)
9.5.1 The Transfer Process of Graphene on the Si/SiO2 Substrate
260(1)
9.5.2 CNT Fabrications
261(1)
9.6 Application of Nanomaterials
261(24)
9.6.1 Graphene Nanoribbon Interconnect
261(13)
9.6.1.1 Geometry of MLGNR Interconnect
263(2)
9.6.1.2 Equivalent MTL Model of MLGNR Interconnect
265(2)
9.6.1.3 ESC Model of MLGNR Interconnect
267(1)
9.6.1.4 Validation of MTL and ESC Model
268(1)
9.6.1.5 Simulation Setup of MLGNR
269(1)
9.6.1.6 Crosstalk-Induced Delay Analysis
270(4)
9.6.2 Carbon Nanotube-Based Interconnect
274(8)
9.6.2.1 Interconnect Model
275(3)
9.6.2.2 Performance Comparison
278(4)
9.6.3 Nanosensor
282(1)
9.6.3.1 Flexible Sensor
282(1)
9.6.3.2 Nanosensor for Biomedical Applications
282(1)
9.6.4 Nanomaterial-Based Combat Jackets
283(1)
9.6.5 Nano-Biosensors for Drug Delivery
284(1)
9.7 Summary
285(1)
9.8 Multiple-Choice Questions
285(3)
9.9 Short Answer Questions
288(1)
9.10 Long Answer Questions
288(1)
References
288(7)
Chapter 10 Nanoscale Transistors 295(24)
10.1 Issues with CMOS Technology Scaling
295(3)
10.1.1 Velocity Saturation and Mobility Degradation
295(1)
10.1.2 Tunneling Limit
295(1)
10.1.3 High Field Effects
296(1)
10.1.4 Power Limitation
297(1)
10.1.5 Material Limitation
297(1)
10.2 Tunnel FET
298(4)
10.2.1 Device Structure and Models
298(1)
10.2.2 Device Characteristics
298(3)
10.2.2.1 TFET as ON Switch
299(1)
10.2.2.2 Ambipolar Characteristics
299(1)
10.2.2.3 Unidirectional Characteristics and p-i-n Forward Leakage
300(1)
10.2.3 TFET-Based Circuit Design
301(1)
10.2.3.1 TFET-Based Static Complementary Inverter Design
301(1)
10.2.3.2 TFET-Based Digital Buffer Design
302(1)
10.3 Negative Capacitance FET
302(4)
10.3.1 Device Structure
303(1)
10.3.2 Principle of Operation
304(1)
10.3.3 Low Subthreshold Swing and High ON Current
304(1)
10.3.4 Hysteresis Characteristics
305(1)
10.3.5 NCFET Device-Based Inverter and Digital Logic Design
306(1)
10.4 Carbon Nanotube FET
306(2)
10.4.1 Carbon Nanotube
307(1)
10.4.2 Carbon Nanotube FET
307(1)
10.4.3 Device Characteristics
307(1)
10.5 Graphene Nanoribbon FET
308(3)
10.5.1 Graphene Structure and Properties
309(1)
10.5.1.1 Mechanical Properties
309(1)
10.5.1.2 Electrical Properties
309(1)
10.5.2 Graphene Nanoribbon FET
309(2)
10.5.2.1 Graphene Nanoribbon
309(1)
10.5.2.2 Graphene Nanoribbon FET
310(1)
10.6 Spintronic Devices
311(3)
10.6.1 Principle of Operation
311(1)
10.6.2 Spin-Based Devices
312(2)
10.6.2.1 STT MTJs
312(1)
10.6.2.2 GSHE-Based Devices
313(1)
10.6.2.3 ASL Devices
313(1)
10.7 Summary
314(1)
10.8 Multiple-Choice Questions
314(1)
10.9 Short Answer Questions
315(1)
10.10 Long Answer Questions
316(1)
References
316(3)
MCQ Answers 319
Index 32
Manoj Kumar Majumder received his PhD from Microelectronics and VLSI group at Indian Institute of Technology, Roorkee, India. Currently, he is working as assistant professor in Department of Electronics and Communication Engineering, IIIT Naya Raipur, Chhattisgarh. He has authored more than 25 papers in peer-reviewed international journals and more than 40 papers in international conferences. He has co-authored a book titled Carbon Nanotobe Based VLSI Interconnects-Analysis and Design (New York, NY, USA: Springer, 2014) and a book-chapter published by CRC Press. His current research interests include the area of graphene based Low power VLSI devices and circuits, On-chip VLSI interconnects and Through silicon vias. Dr. Majumder is associated with different academic and administrative activities of different positions in IIIT, Naya Raipur. He is an active member of IEEE, IEEE Electron Device Society and IEEE Circuits and Systems Society. He had delivered technical talks at different conferences in India and abroad. He is also an active reviewer of IEEE Transactions on electromagnetic Compatibility, IEEE Transactions on Nanotechnology, IEEE Electron Device Letters, Microelectronics Journal, IET Micro & Nano Letters, and other Springer Journals. He is a Member of many expert committees constituted by Government and Nongovernment organizations. He has also received many awards and recognitions from International Biographical Center, Cambridge, etc. His name has been listed in Marquis Whos Who in the World. Vijay Rao Kumbhare received the B.Tech degree in Electronics and Telecommunication Engineering from National Institute of Technology, Raipur, India in 2008, and M.Tech degree with specialization of Telecommunication System Engineering (TSE) under Electronics and Engineering Communication Department from Indian Institute of Technology, Kharagpur, West Bengal, India, in 2011. He had worked experience as assistant professor more than 5 years. He is currently working toward the Ph.D degree from Dr. Shyama Prasad Mukherjee International Institute of Information Technology Naya Raipur, India. He has attended several workshop and conferences, along with an active reviewer of reputed IET Biotechnology. His current research interest are in the area of Graphene nanoribbon, Carbon nanotube and optical based On-chip VLSI interconnects, emerging nano-materials. Aditya Japa received B.Tech. degree in Electronics and Communication Engineering from Sree Chaitanya College of Engineering, Karimnagar (J.N.T.U Hyderabad), Telangana, India, in 2012 and the M.Tech. degree in VLSI Design from Vignans University, Andhra Pradesh, India, in 2015. He was a JRF under a DST project titled Design, Analysis and Benchmarking of Energy efficient Hetero-junction tunnel FET based Digital, Analog and RF Building blocks during 2015-16. He is currently pursuing Ph.D. in Electronics and Communication Engineering from DSPM International Institute of Information Technology, Naya Raipur, India. His current research interest includes Hardware security subsystems like TRNG and PUF, emerging transistor technologies (Tunnel FETs), ultra-low power/energy efficient sensor readout circuits, VLSI design etc. Brajesh Kumar Kaushik received his Doctorate of Philosophy (Ph.D.) in 2007 from Indian Institute of Technology, Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor. He has extensively published in several national and international journals and conferences. He is a reviewer of many international journals belonging to various publishers including IEEE, IET, Elsevier, Springer, Taylor & Francis, Emerald, ETRI, and PIER. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. He holds the position of Editor and Editor-in-Chief of various journals in the field of VLSI and microelectronics such as International Journal of VLSI Design & Communication Systems (VLSICS), AIRCC Publishing Corporation. He also holds the position of Editor of Microelectronics Journal (MEJ), Elsevier Inc.; Journal of Engineering, Design and Technology (JEDT), Emerald Group Publishing Limited; Journal of Electrical and Electronics Engineering Research (JEEER); and Academic Journals. He has received many awards and recognitions from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Whos Who in Science and Engineering® and Marquis Whos Who in the World®. Dr. Kaushik has been conferred with Distinguished Lecturer award of IEEE Electron Devices Society (EDS) to offer EDS Chapters with a list of quality lectures in his research domain.