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IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection 1st ed. 2016 [Kõva köide]

  • Formaat: Hardback, 154 pages, kõrgus x laius: 235x155 mm, kaal: 3731 g, IX, 154 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 08-Sep-2015
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319220349
  • ISBN-13: 9783319220345
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IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection 1st ed. 2016Suurem pilt
  • Formaat: Hardback, 154 pages, kõrgus x laius: 235x155 mm, kaal: 3731 g, IX, 154 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 08-Sep-2015
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319220349
  • ISBN-13: 9783319220345
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783319220345.html
Märksõnad:
This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author"s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies.Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection;Introduce a deep introduction for Verilog for both implementation and verification point of view.Demonstrates how to use IP in applications such as memory controllers and SoC buses.Describes a new verification methodology called bug localization;Prese

nts a novel scan-chain methodology for RTL debugging;Enables readers to employ UVM methodology in straightforward, practical terms.

1. Introduction.- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection.- 3. Analyzing the Trade-off between Different Memory Cores and Controllers.- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES.- 5. Verilog for Implementation and Verification.- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation.- 7. Conclusions.
1 Introduction
1(12)
References
11(2)
2 IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection
13(38)
2.1 Introduction
13(1)
2.2 IP Modeling
13(14)
2.2.1 FPGA
15(8)
2.2.2 Processor
23(2)
2.2.3 ASIC
25(2)
2.2.4 PCB
27(1)
2.3 IP Verification
27(10)
2.3.1 FPGA-Based/Processor-Based IP Verification
28(8)
2.3.2 ASIC-Based IP Verification
36(1)
2.3.3 PCB-Based IP Verification
37(1)
2.4 IP Optimization
37(10)
2.4.1 FPGA-Based IP Optimization
37(7)
2.4.2 Processor-Based IP Optimization
44(1)
2.4.3 ASIC-Based IP Optimization
45(1)
2.4.4 PCB-Based IP Optimization
46(1)
2.5 IP Protection
47(1)
2.5.1 FPGA-Based/Processor-Based IP Protection
47(1)
2.5.2 ASIC-Based IP Protection
47(1)
2.5.3 PCB-Based IP Protection
48(1)
2.6 Summary
48(3)
References
49(2)
3 Analyzing the Trade-off Between Different Memory Cores and Controllers
51(26)
3.1 Introduction
51(1)
3.2 Memory Cores
52(5)
3.3 Why Standards?
57(1)
3.4 Memory Controllers
58(6)
3.5 Comparison Between Different Memory Controllers
64(9)
3.6 New Trends in SoC Memories
73(1)
3.7 Summary
73(4)
References
76(1)
4 SoC Buses and Peripherals: Features and Architectures
77(20)
4.1 Introduction
77(1)
4.2 SoC Buses and Peripherals Background
78(2)
4.3 SoC Buses: Features and Architectures
80(11)
4.3.1 SoC Bus Topology
80(3)
4.3.2 Arbitration (Mux/Tri-State-Based)
83(3)
4.3.3 Transfers
86(3)
4.3.4 Timing
89(1)
4.3.5 Tx Control
90(1)
4.3.6 Tx Type
90(1)
4.4 Bus Architecture Examples
91(4)
4.4.1 I2C Bus
91(2)
4.4.2 Advanced Microcontroller Bus Architecture (AMBA)
93(2)
4.4.3 Wishbone
95(1)
4.5 Summary
95(2)
References
96(1)
5 Verilog for Implementation and Verification
97(24)
5.1 Introduction
97(1)
5.2 Verilog for Implementation
98(10)
5.2.1 Introduction
98(3)
5.2.2 Data Representation
101(1)
5.2.3 Verilog Coding Style
102(1)
5.2.4 Verilog Operators and Control Constructs
103(3)
5.2.5 Verilog Design Issues
106(1)
5.2.6 Verilog Template and Reusable Code Tips
106(2)
5.2.7 Main Digital System Building Blocks
108(1)
5.3 Verilog for Verification
108(3)
5.4 Logic Simulators
111(7)
5.4.1 Questa Simulation
112(2)
5.4.2 Questa Formal Verification
114(1)
5.4.3 Questa CoverCheck
114(1)
5.4.4 Questa CDC
115(1)
5.4.5 Questa ADMS
115(1)
5.4.6 Questa inFACT
116(1)
5.4.7 Questa Power Aware Simulation
116(1)
5.4.8 Questa Verification IP
117(1)
5.4.9 Questa Verification Management
117(1)
5.4.10 Questa CodeLink
118(1)
5.5 Summary
118(3)
References
118(3)
6 New Trends in SoC Verification: UVM, Bug Localization, Scan-C0068ain-Based Methodology, GA-Based Test Generation
121(32)
6.1 Part I: UVM
121(12)
6.1.1 Introduction
121(2)
6.1.2 System Verilog
123(3)
6.1.3 TLM
126(1)
6.1.4 UVM
127(6)
6.1.5 Summary
133(1)
6.2 Part II: RTL Bug Localization
133(8)
6.2.1 Introduction
133(2)
6.2.2 RTL Bug Localization
135(3)
6.2.3 Summary
138(3)
6.3 Part III: RTL Scan-Chain
141(3)
6.3.1 Introduction
141(1)
6.3.2 The Proposed RTL-Level Scan-Chain Methodology
141(2)
6.3.3 Summary
143(1)
6.4 Part IV: Automatic Test Generation Based on Genetic Algorithms
144(9)
6.4.1 Introduction
144(2)
6.4.2 Proposed Methodology
146(4)
6.4.3 Summary
150(1)
References
150(3)
7 Conclusions
153
Dr. Khaled Salah attended the school of engineering, Department of Electronics and Communications at Ain-Shams University, Egypt, from 1998 to 2003, where he received his B.Sc. degree in Electronics and Communications Engineering with distinction and honor degree. He received his M.Sc. and his Ph.D. degrees in Electronics and Communications in 2008, 2012 respectively. He joined Mentor Graphic Corporation, where he designed many SoC IPs such as AHB, HDMI, HDCP, eMMC, SDcard, HMC. Currently, Dr. Khaled Salah is a Technical Lead at the Emulation division at Mentor Graphic, Egypt. Dr. Khaled Salah has published one book and more than 42 research papers in the top refereed journals and conferences. His research interests are in 3D integration, IP Modeling, and SoC design.