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Language-driven Exploration and Implementation of Partially Re-configurable ASIPs 2009 ed. [Kõva köide]

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  • Formaat: Hardback, 203 pages, kõrgus x laius: 235x156 mm, kaal: 1060 g, IX, 203 p., 1 Hardback
  • Ilmumisaeg: 10-Dec-2008
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1402092962
  • ISBN-13: 9781402092961
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Language-driven Exploration and Implementation of Partially Re-configurable ASIPs 2009 ed.Suurem pilt
  • Formaat: Hardback, 203 pages, kõrgus x laius: 235x156 mm, kaal: 1060 g, IX, 203 p., 1 Hardback
  • Ilmumisaeg: 10-Dec-2008
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1402092962
  • ISBN-13: 9781402092961
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781402092961.html
Märksõnad:
Increasing complexity of embedded systems demands system designers to ramp up their design productivity without compromising performance goals which is done by Electronic System Level (ESL) techniques. This book addresses a segment of the ESL area by modeling partially re-configurable processors via high-level Architecture Description Language.

Increasing complexity of modern embedded systems demands system designers to ramp up their design productivity without compromising performance goals. This is promoted by modern Electronic System Level (ESL) techniques. Language-driven Exploration and Implementation of Partially Re-configurable ASIPs addresses an important segment of the ESL area by modeling partially re-configurable processors via high-level Architecture Description Language (ADL). This approach also hints an imminent evolution in the area of re-configurable system design.
1 Introduction 1
2 Background 5
2.1 Processor Design: A Retrospection
5
2.2 High-level Processor Modelling
7
2.3 Library-Based Processor Design
11
2.4 Partially Re-configurable Processors: A Design Alternative
13
2.5 Synopsis
16
3 Related Work 17
3.1 A Chronological Overview of the Expanding rASIP Design Space
17
3.2 rASIP Design: High-level Modelling Approach
29
3.3 rASIP Design: Library-based Approach
31
3.4 Independent rASIP Design Tools
33
3.4.1 Profiling
33
3.4.2 Automated Kernel Synthesis
34
3.5 Motivation
36
3.6 Synopsis
37
4 rASIP Design Space 39
4.1 Architecture Design Points
39
4.1.1 ASIP Architecture
40
4.1.2 Re-Configurable Block Architecture
49
4.1.3 Interface
56
4.2 Language-Based rASIP Modelling
57
4.2.1 Intuitive Modelling Idea
57
4.2.2 ISA Modelling
58
4.2.3 Structure Modelling: Base Processor
60
4.2.4 Structure Modelling: FPGA Description
62
4.3 Language-based rASIP Design Flow
65
4.3.1 Pre-fabrication Design Flow
65
4.3.2 Post-fabrication Design Flow
67
4.4 Synopsis
68
5 Pre-Fabrication Design Space Exploration 71
5.1 Pre-Fabrication Design Decisions
72
5.2 Application Characterization
73
5.2.1 Quantifiable Characteristics
74
5.2.2 Non-Quantifiable Characteristics
74
5.3 Software Tool-Suite Generation for rASIP
77
5.3.1 ISS Generation for rASIP
78
5.3.2 C Compiler Generation for rASIP
82
5.4 Partitioning the ISA: Coding Leakage Exploration
85
5.4.1 Coding Leakage Determination Algorithm
88
5.5 Synopsis
91
6 Pre-Fabrication Design Implementation 93
6.1 Base Processor Implementation
94
6.1.1 IR Definition
95
6.1.2 IR Construction
97
6.1.3 Back-End for HDL Generation
98
6.2 Partitioning the Structure: Specification Aspects
98
6.2.1 LISA Language Extensions for Partitioning: Recapitulation
98
6.3 Partitioning the Structure: Implementation Aspects
101
6.3.1 Unit Movement
101
6.3.2 Re-Configurable Unit and Pipeline
102
6.3.3 Register Localization
103
6.3.4 Decoder Localization
103
6.4 Latency: Multiple Clock Domain Implementation
105
6.4.1 Synchronizing Clock Domains Using Flancter
106
6.4.2 Modifications for rASIP
107
6.5 Automatic Interface Generation and Storage
107
6.6 Background for FPGA Implementation
108
6.6.1 Re-Configurable Part of rASIP: DFG-Based Representation
109
6.6.2 LISA Language Extensions for FPGA Description: Recapitulation
112
6.6.3 Internal Storage of the FPGA Structural Description
112
6.6.4 Coarse-Grained FPGA Architecture Implementation from High-Level Specification: Related Work
115
6.7 FPGA Implementation: RTL Synthesis
115
6.7.1 Synthesis Beyond RTL
118
6.8 Background for Synthesis on FPGA
119
6.8.1 Synthesis on Coarse-Grained FPGA Architecture: Related Work
123
6.9 FPGA Synthesis: Mapping and Clustering
124
6.10 FPGA Synthesis: Placement and Routing
132
6.10.1 Configuration Bitstream Generation
135
6.10.2 Synthesis on Non-Clustered Heterogeneous FPGA
137
6.11 Synopsis
138
7 Post-fabrication Design Space Exploration and Implementation 139
7.1 Post-fabrication Design Space Exploration
139
7.1.1 Integration with Custom Instruction Synthesis Tool
140
7.1.2 Re-targeting Software Toolsuite
142
7.2 Post-fabrication Design Implementation
142
7.2.1 Interface Matching
143
7.2.2 Area-Optimized Coarse-Grained FPGA Synthesis
144
7.3 Synopsis
146
8 Case Study 149
8.1 Introduction
149
8.2 Experiments with RISC-Based Architecture
149
8.3 Experiments with VLIW-Based Architecture
153
8.4 Experiments with Coarse-Grained FPGA Exploration
158
8.5 rASIP Modelling for WCDMA
164
8.5.1 Profiling
165
8.5.2 Base Architecture
166
8.5.3 Hardware Extensions
167
8.5.4 Instruction Set Architecture Extensions
167
8.5.5 Software Extensions
169
8.5.6 Synthesis Results
170
8.5.7 Extending Towards rASIP
170
8.5.8 Coarse-Grained FPGA Exploration for SIMD_CMAC
172
8.6 Study on Design Space Exploration Efficiency
175
8.6.1 MPEG2 IDCT Kernel
176
8.6.2 JPEG IDCT and DCT Kernels
178
8.6.3 SAD Kernel
178
8.6.4 SHTD Kernel
178
9 Past, Present and Future 181
9.1 Past
181
9.2 Present
183
9.2.1 Pre-Fabrication Design Flow
183
9.2.2 Post-fabrication Design Flow
185
9.3 Future
186
References 189
A LISA Grammar for Coarse-Grained FPGA 201