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Logic Non-volatile Memory: The Nvm Solutions For Ememory [Kõva köide]

(Ememory Technology, Inc., Taiwan), (Ememory Technology, Inc., Taiwan), (Founder & Chairman Of Ememory Technology Inc., Taiwan)
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Logic Non-volatile Memory: The Nvm Solutions For EmemorySuurem pilt
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Püsilink: https://www.kriso.ee/db/9789814460903.html
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Contributors from the eMemory Technology company in Taiwan argue that for all the mobile, tablet, and cloud computing, non-volatile memory is still the only solution for the long-term storage of essential system information and data when the power supply is turned off. They detail four technologies the company offers. The topics are one time programmable (OTP) memory, flash, electrically erasable programmable read only memory (EEPROM), and non-volatile memory intellectual property foundry. For each they discuss the device, process integration reliability, design, test flow and characterization, qualification, applications, and other matters as appropriate. Annotation ©2014 Ringgold, Inc., Portland, OR (protoview.com)

ntegrated logic circuits, and as a trimming sector in your high voltage driver and other silicon integrated analog circuits? Would you like to learn how to embed the NVM into your silicon integrated circuit products to improve their performance? This book is written to help you.It provides comprehensive instructions on fabricating the NVM using the same processes you are using to fabricate your logic integrated circuits. We at our eMemory company call this technology the embedded Logic NVM. Because embedded Logic NVM has simple fabrication processes, it has replaced the conventional NVM in many traditional and new applications, including LCD driver, LED driver, MEMS controller, touch panel controller, power management unit, ambient and motion sensor controller, micro controller unit (MCU), security ID setting tag, RFID, NFC, PC camera controller, keyboard controller, and mouse controller. The recent explosive growth of the Logic NVM indicates that it will soon dominate all NVM applications. The embedded Logic NVM was invented and has been implemented in users' applications by the 200+ employees of our eMemory company, who are also the authors and author-assistants of this book.This book covers the following Logic NVM products: One Time Programmable (OTP) memory, Multiple Times Programmable (MTP) memory, Flash memory, and Electrical Erasable and Programmable Read Only Memory (EEPROM). The fundamentals of the NVM are described in this book, which include: the physics and operations of the memory transistors, the basic building block of the memory cells and the access circuits.All of these products have been used continuously by the industry worldwide. In-depth readers can attain expert proficiency in the implementation of the embedded Logic NVM technology in their products.
Foreword v
Preface vii
Acknowledgements xv
List of Figures xxvii
List of Tables xxxiii
Chapter 1 Introduction
1.1 What Are Logic NVMs
3(2)
1.2 When to Use Logic NVM
5(1)
1.3 Why Use Logic NVM
6(2)
1.4 Which Logic NVM is Better to Use
8(1)
1.5 Where to Get the Logic NVM Platform
9(2)
1.6 How to Use Logic NVM
11(2)
References
13(4)
Chapter 2 One Time Programmable (OTP) Memory
2.1 OTP (NeoBit) Cell
17(11)
2.1.1 Cell Structure,
17(1)
2.1.2 Why pMOST,
18(2)
2.1.3 Programming Mechanism,
20(2)
2.1.4 Erase Mechanism,
22(1)
2.1.5 Read Operation,
22(2)
2.1.6 Data Retention,
24(3)
2.1.7 Program Disturb,
27(1)
2.1.8 Read Disturb,
27(1)
2.2 Process Integration
28(2)
2.2.1 Gate Oxide Formation,
29(1)
2.2.2 Contact Etch Stop Layer Capacitor Deposition,
29(1)
2.2.3 BEOL Tungsten CMP and High-Density-Plasma Oxide Deposition,
29(1)
2.2.4 Ultraviolet Transparent Passivation Layer Deposition,
30(1)
2.3 Reliability
30(16)
2.3.1 Accelerated Life Test,
30(1)
2.3.2 Acceleration Factor,
31(3)
2.3.3 Semiconductor Device Failure Regions,
34(3)
2.3.4 Gate Oxide Reliability - Time-Dependent Dielectric Breakdown (TDDB),
37(8)
2.3.4.1 E Model,
38(1)
2.3.4.2 1/E Model,
39(1)
2.3.4.3 V Model,
40(1)
2.3.4.4 TDDB Numerical Example Using V Model,
40(3)
2.3.4.5 Power-Law Model,
43(1)
2.3.4.6 Scaling Factor,
44(1)
2.3.5 High Temperature Data Retention - Ea Value Extrapolation,
45(1)
2.4 Design
46(9)
2.4.1 Array Architecture,
48(1)
2.4.2 Sense Amplifier,
49(4)
2.4.3 Fuse-Type Sense Amplifier,
53(2)
2.5 Introduction for ESD Protection on Non-Volatile Memories
55(4)
2.6 Test Flow and Characterization
59(11)
2.6.1 Test Flow,
59(5)
2.6.1.1 Full Test Flow,
59(2)
2.6.1.2 Program Code Stages,
61(1)
2.6.1.3 Wafer Sort Flow,
62(1)
2.6.1.4 Special Notes,
63(1)
2.6.2 Characterization,
64(6)
2.6.2.1 DC Characterization,
64(3)
2.6.2.2 AC Characterization,
67(1)
2.6.2.3 Retention Performance,
68(1)
2.6.2.4 UV Erase Performance,
69(1)
2.6.2.5 Conclusion,
70(1)
2.7 Qualification
70(7)
2.7.1 OTP Qualification Plan,
71(4)
2.7.2 OTP Qualification Flow,
75(2)
2.8 Application
77(4)
2.9 IP Specifications
81(2)
2.10 Multiple Times Programmable (MTP) Derivatives
83(1)
2.11 OTP to ROM Conversion
84(3)
References
87(6)
Chapter 3 Flash
3.1 Device
93(32)
3.1.1 Basic Cell Structure,
94(2)
3.1.2 Program Operation,
96(8)
3.1.3 Erase Operation,
104(3)
3.1.4 Read Operation,
107(1)
3.1.5 Array Architecture,
108(1)
3.1.6 Array Disturb,
109(3)
3.1.7 Endurance,
112(1)
3.1.8 Data Retention,
113(3)
3.1.9 Operation Window,
116(2)
3.1.10 Ramping CL PGM Scheme,
118(7)
3.2 Process Integration
125(9)
3.2.1 Isolation,
129(1)
3.2.2 Deep n-Well (DNW) Process,
130(1)
3.2.3 ONO Film Formation,
131(2)
3.2.4 Poly Gate Formation,
133(1)
3.2.5 Reverse ONO Etch,
134(1)
3.3 Reliability
134(9)
3.3.1 Gate Oxide Reliability - Time-Dependent Dielectric Breakdown (TDDB),
135(3)
3.3.2 Endurance,
138(1)
3.3.3 High Temperature Data Retention - Ea Value Extrapolation,
139(4)
3.4 Design
143(18)
3.4.1 Read/Write Cell Bias Condition,
143(5)
3.4.1.1 Read Operation Cell Bias,
145(2)
3.4.1.2 Write Operation Cell Bias,
147(1)
3.4.2 Block Diagram of NeoFlash IP,
148(1)
3.4.3 Decoding System Introduction,
149(2)
3.4.4 Sense Amplifier,
151(1)
3.4.5 PGM/ERS with PV/EV Scheme,
152(2)
3.4.6 HV System Introduction,
154(1)
3.4.7 Charge Pumping Circuit,
155(3)
3.4.8 Test Mode Function Introduction,
158(3)
3.5 Test Flow and Characterization
161(13)
3.5.1 Test Flow,
161(5)
3.5.2 Characterization,
166(8)
3.6 Qualification
174(4)
3.7 Applications
178(1)
3.8 IP Specifications
178(2)
3.9 Flash to ROM Conversion
180(1)
References
181(4)
Chapter 4 EEPROM
4.1 Device
185(41)
4.1.1 EEPROM (Electrically Erasable Programmable Read Only Memory),
185(5)
4.1.2 Nitride Storage Solutions,
190(13)
4.1.2.1 Toshiba,
190(1)
4.1.2.2 Fujitsu,
191(2)
4.1.2.3 IBM,
193(2)
4.1.2.4 Tower Semiconductor (S-Flash),
195(2)
4.1.2.5 NTHU (SAN),
197(3)
4.1.2.6 Challenges for Nitride Storage Solutions,
200(3)
4.1.3 Floating Gate Solutions,
203(14)
4.1.3.1 Toshiba,
203(1)
4.1.3.2 IBM,
204(2)
4.1.3.3 Bell Labs,
206(2)
4.1.3.4 Impinj,
208(2)
4.1.3.5 Tower Semiconductor,
210(1)
4.1.3.6 Yield Microelectronics Corp. (YMC),
211(4)
4.1.3.7 Challenges of Floating Gate Solutions,
215(2)
4.1.4 NeoEE Technology,
217(9)
4.1.4.1 Device Operation,
218(3)
4.1.4.2 Device Characterization and Reliability,
221(3)
4.1.4.3 BYTE-Erasable EEPROM Architecture,
224(2)
4.2 Process Integration
226(6)
4.2.1 HV Devices, Rules & Reliability,
226(4)
4.2.2 Logic Circuit Manufacturing Process Derivatives,
230(1)
4.2.3 Challenges at Advanced Technology Nodes,
231(1)
4.3 NeoEE Design Introduction
232(16)
4.3.1 NeoEE Design Challenges,
232(2)
4.3.2 NeoEE Array Architecture,
234(2)
4.3.3 NeoEE READ Design,
236(1)
4.3.4 NeoEE HV Design,
237(10)
4.3.4.1 NeoEE HV Power Generation,
238(2)
4.3.4.2 NeoEE HV Power Delivery,
240(7)
4.3.5 NeoEE Test Mode Design,
247(1)
4.4 Characterization and Reliability
248(1)
4.5 Applications
249(1)
4.6 IP Specifications
249(2)
References
251(4)
Chapter 5 Non-Volatile Memory IP Foundry
5.1 IP Developing Flow
255(4)
5.1.1 Marketing Survey,
255(1)
5.1.2 Process Development and Qualification,
256(1)
5.1.3 IP Design and Production,
257(2)
5.2 IP Design and Layout Flow
259(3)
5.2.1 Project Feasibility Assessment,
259(1)
5.2.2 Project Planning,
259(1)
5.2.3 Design and Layout Implementation,
260(1)
5.2.4 Silicon Fabrication,
261(1)
5.2.5 IP Function Verification,
261(1)
5.2.6 IP Reliability Qualification,
262(1)
5.3 IP Service Flow
262(2)
5.4 IP Deliverables and Security
264(2)
5.4.1 IP Design Kits,
264(1)
5.4.2 IP Tape-Out Kits,
265(1)
5.5 Intelligent System for IP Production
266(3)
Index 269