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Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS 2006 ed. [Kõva köide]

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Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS 2006 ed.Suurem pilt
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Püsilink: https://www.kriso.ee/db/9781402041396.html
Märksõnad:
Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS addresses the low-power low-voltage Sigma-Delta ADC design in nanometer CMOS technologies at both the circuit-level and the system level.The low-power low-voltage Sigma-Delta modulator design at the circuit level is introduced. A design example is presented in this book. This design is the first published Sigma-Delta design in a 90-nm CMOS technology and reaches a very high figure-of-merit. At the system level, a novel systematic study on the full feedforward Sigma-Delta topology is presented in this book. As a design example, a fourth-order single-loop full feedforward Sigma-Delta modulator design in a 130-nm pure digital CMOS technology is presented. This design is the first design using the full feedforward Sigma-Delta topology and reaches the highest conversion speed among all the 1-V Sigma-Delta modulators to date.

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List of Tables
xi
List of Figures
xiii
Symbols and Abbreviations xxi
Physical xxi
Definitions xxi
Introduction
1(2)
Motivation
1(1)
Outline of the Work
2(1)
ADCs in Nanometer CMOS Technologies
3(16)
Introduction
3(1)
Scaling-Down of CMOS Technologies
3(3)
Driving Force of the CMOS Scaling-Down
4(1)
Moving into Nanometer CMOS Technologies
5(1)
Impact of Moving into Nanometer CMOS to Analog Circuits
6(5)
Decreased Supply Voltage
6(1)
Impact on Transistor Intrinsic Gain
7(2)
Impact on Device Matching
9(1)
Impact on Device Noise
10(1)
ADCs in Nanometer CMOS
11(6)
Decreased Signal Swing
13(1)
Degraded Transistor Characteristics
13(1)
Distortion
14(1)
Switch Driving
14(3)
Improved Device Matching
17(1)
Digital Circuits Advantages
17(1)
Conclusion
17(2)
Principle of Σ-Δ ADC
19(28)
Introduction
19(1)
Basic Analog to Digital Conversion
19(5)
Oversampling and Noise Shaping
24(9)
Oversampling
25(1)
Noise Shaping
26(3)
Σ-Δ Modulator
29(2)
Performance Metrics for the Σ-Δ ADC
31(2)
Traditional Σ-Δ ADC Topology
33(13)
Single-Loop Single-Bit Σ-Δ Modulators
33(4)
Single-Loop Multibit Σ-Δ Modulators
37(2)
Cascaded Σ-Δ Modulators
39(7)
Performance Comparison of Traditional Σ-Δ Topologies
46(1)
Conclusion
46(1)
Low-Power Low-Voltage Σ-Δ ADC Design in Nanometer CMOS: Circuit Level Approach
47(52)
Introduction
47(1)
Low-Voltage Low-Power OTA Design
48(18)
Gain Enhanced Current Mirror OTA Design
49(4)
A Test Gain-Enhanced Current Mirror OTA
53(1)
Implementation and Measurement Results
54(1)
Two-Stage OTA Design
55(11)
Low-Voltage Low-Power Σ-Δ ADC Design
66(10)
Impact of Circuit Nonidealities to Σ-Δ ADC Performance
66(1)
Modulator Topology Selection
67(2)
OTA Topology Selection
69(6)
Transistor Biasing
75(1)
Scaling of Integrators
75(1)
A 1-V 140-μW Σ-Δ Modulator in 90-nm CMOS
76(11)
Building Block Circuits Design
76(4)
Implementation
80(2)
Measurement Results
82(5)
Measurements on PSRR and Low-Frequency Noise Floor
87(9)
Introduction of PSRR
87(1)
PSRR Measurement Setup
88(1)
PSRR Measurement Results
88(7)
Measurement on Low-Frequency Noise Floor
95(1)
Conclusion
96(3)
Low-Power Low-Voltage Σ-Δ ADC Design in Nanometer CMOS: System Level Approach
99(50)
Introduction
99(1)
The Full Feedforward Σ-Δ ADC Topology
100(15)
Single-Loop Single-Bit Full Feedforward Σ-Δ Modulators
101(6)
Single-Loop Multibit Full Feedforward Σ-Δ Modulators
107(3)
Cascaded Full Feedforward Σ-Δ Modulators
110(5)
Performance Comparison of Full Feedforward Σ-Δ Topologies
115(1)
Linearity Analysis of Σ-Δ ADC
115(4)
Non-Linearities Modeling in Σ-Δ ADC
116(1)
Non-Linear OTA Gain Modeling in Σ-Δ ADC
117(1)
Linearity Performance Comparison
117(2)
Circuit Implementation of the Full Feedforward Σ-Δ Modulator
119(5)
A 1.8-V 2-MS/s Σ-Δ Modulator in 180-nm CMOS
124(7)
Implementation
124(7)
Measurement results
131(1)
A 1-V 1-MS/s Σ-Δ Modulator in 130-nm CMOS
131(6)
Implementation
131(2)
Measurement Results
133(4)
Multibit Full Feedforward Σ-Δ Modulator Design
137(6)
Optimized Loop Coefficients
138(1)
Circuit Implementation
139(4)
Conclusion
143(6)
Conclusions
149(2)
Bibliography 151(6)
Index 157


Prof. Michiel Steyaert received his Ph.D. degree in electronics from the Katholieke Universiteit Leuven (KUL) in June 1987. In 1988 he was an associated assistant professor at the U.C.L.A. From 1989 he joined the ESAT-MICAS group at the KUL, were he is now a Full Professor. His current research interests are in analog integrated circuits for high-frequency telecommunication systems and high performance analog signal processing. He authored or co-authored over 250 papers and co-authored over 5 books. He received the 1990 European Solid-State Circuits Conference Best Paper Award, the 1995 and 1997 ISSCC Evening Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award and the 1991 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications.