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Low-Power Wireless Communication Circuits and Systems: 60GHz and Beyond [Kõva köide]

(Nanyang Technological University, Singapore), (Singapore University of Technology and Design)
  • Formaat: Hardback, 358 pages, kõrgus x laius: 229x152 mm, kaal: 820 g, 14 Tables, black and white; 7 Illustrations, color; 177 Illustrations, black and white
  • Ilmumisaeg: 26-Apr-2018
  • Kirjastus: Pan Stanford Publishing Pte Ltd
  • ISBN-10: 9814745960
  • ISBN-13: 9789814745963
Teised raamatud teemal:
Low-Power Wireless Communication Circuits and Systems: 60GHz and BeyondSuurem pilt
  • Formaat: Hardback, 358 pages, kõrgus x laius: 229x152 mm, kaal: 820 g, 14 Tables, black and white; 7 Illustrations, color; 177 Illustrations, black and white
  • Ilmumisaeg: 26-Apr-2018
  • Kirjastus: Pan Stanford Publishing Pte Ltd
  • ISBN-10: 9814745960
  • ISBN-13: 9789814745963
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9789814745963.html
Märksõnad:

The increasing demand for extremely high-data-rate communications has urged researchers to develop new communication systems. Currently, wireless transmission with more than one Giga-bits-per-second (Gbps) data rates is becoming essential due to increased connectivity between different portable and smart devices. To realize Gbps data rates, millimeter-wave (MMW) bands around 60 GHz is attractive due to the availability of large bandwidth of 9 GHz.

Recent research work in the Gbps data rates around 60 GHz band has focused on short-range indoor applications, such as uncompressed video transfer, high-speed file transfer between electronic devices, and communication to and from kiosk. Many of these applications are limited to 10 m or less, because of the huge free space path loss and oxygen absorption for 60 GHz band MMW signal.

This book introduces new knowledge and novel circuit techniques to design low-power MMW circuits and systems. It also focuses on unlocking the potential applications of the 60 GHz band for high-speed outdoor applications. The innovative design application significantly improves and enables high-data-rate low-cost communication links between two access points seamlessly. The 60 GHz transceiver system-on-chip provides an alternative solution to upgrade existing networks without introducing any building renovation or external network laying works.

Preface xiii
Acknowledgments xv
1 Introduction
3(18)
Kaixue Ma
Kiat Seng Yeo
1.1 Background and Motivation
3(6)
1.2 Contributions
9(3)
1.3 Scope and Organization
12(9)
2 Fundamentals of Circuit Networks
21(18)
Wei Xu
Kaixue Ma
Kiat Seng Yeo
2.1 Introduction
21(1)
2.2 Two-Port Scattering Matrix
22(1)
2.3 Two-Port Z Matrix
23(1)
2.4 Two-Port Y Matrix
24(1)
2.5 Two-Port ABCD Matrix
24(2)
2.6 Network Connections
26(2)
2.7 Network Conversions
28(1)
2.8 Resonant Network
29(4)
2.9 Even-Odd Mode Analysis
33(1)
2.10 Multi-Port Network
34(5)
3 Active Devices
39(10)
Bharatha Kumar Thangarasu
Kaixue Ma
Kiat Seng Yeo
3.1 Diode
40(1)
3.2 Transistor
41(3)
3.2.1 Transistor Design Consideration for RF and Millimeter-Wave Frequency Applications
43(1)
3.3 BJT versus MOS Transistors and Hybrid Use
44(5)
4 Passive Elements
49(14)
Yongqiang Wang
Kaixue Ma
Kiat Seng Yeo
4.1 Introduction
50(1)
4.2 Resistor
50(2)
4.3 Capacitor
52(2)
4.3.1 MIM Capacitors
52(1)
4.3.2 Interdigital Capacitors
52(2)
4.4 Inductor
54(1)
4.5 Transformer
55(2)
4.6 Interconnects
57(1)
4.7 Transmission Lines
58(5)
5 Variable Gain Amplifier
63(20)
Bharatha Kumar Thangarasu
Kaixue Ma
Kiat Seng Yeo
5.1 Introduction
64(1)
5.2 VGA Design Analysis
64(4)
5.2.1 dB-Linearity
66(1)
5.2.2 DC Offset Cancellation
67(1)
5.3 Variable Gain Amplifier Examples
68(15)
5.3.1 VGA1: Based on 0.18 μm SiGe BiCMOS Programmable Gain Amplifier Design
68(5)
5.3.2 VGA2: Based on 65 nm CMOS Variable Gain Amplifier Design
73(10)
6 Power Amplifier
83(18)
Bharatha Kumar Thangarasu
Kaixue Ma
Kiat Seng Yeo
6.1 Introduction
84(1)
6.2 PA Design Analysis
85(2)
6.2.1 Amplifier Linearity versus Power Added Efficiency
86(1)
6.3 Power Amplifier Examples
87(14)
6.3.1 PA1: Differential Drive Amplifier Based on Variable Gain Control and Frequency-Tunable Load
87(1)
6.3.1.1 Variable gain amplifier stage analysis
87(1)
6.3.1.2 Frequency-tunable amplifier stage analysis
88(3)
6.3.1.3 Frequency-tunable load design
91(1)
6.3.1.4 Q-factor enhancement
91(3)
6.3.2 PA2: Single-Ended Transformer-Based Power Amplifier
94(7)
7 Low-Noise Amplifier
101(20)
Bharatha Kumar Thangarasu
Kaixue Ma
Kiat Seng Yeo
7.1 Introduction
102(1)
7.2 LNA Design Analysis
103(3)
7.2.1 Noise Figure
104(1)
7.2.2 Linearity
104(1)
7.2.3 Variable Gain LNA as a Trade-Off between Low Noise and Good Linearity Performance
105(1)
7.3 Low-Noise Amplifier Examples
106(15)
7.3.1 LNA1: Based on 65 nm CMOS with Custom-Built Inductor
106(2)
7.3.1.1 Marginally stable criteria and gain boosting
108(1)
7.3.1.2 Unstable criteria causing oscillations
108(1)
7.3.1.3 Unconditionally stable criteria
108(5)
7.3.2 LNA2: Based on 0.18 μm SiGe BiCMOS with Distributive Transmission Line Inductor and Interconnect Design
113(8)
8 Bi-Directional Low-Noise Amplifier
121(16)
Bharatha Kumar Thangarasu
Kaixue Ma
Kiat Seng Yeo
8.1 Introduction
122(2)
8.2 BDA Design Analysis
124(3)
8.2.1 Signal Flow Direction Switch Control
125(1)
8.2.2 Interconnect Network Design
126(1)
8.3 Bi-Directional Low-Noise Amplifier Examples
127(10)
8.3.1 BDA1---Based on 65 nm CMOS with Custom-Built Inductor and Micro-Strip Line Three-Port Interconnect Network
127(3)
8.3.2 BDA2---Based on 0.18 μm SiGe BiCMOS with Distributive Transmission Line Inductor and Interconnect Network Design
130(7)
9 Millimeter-Wave Mixer
137(46)
Shouxian Mou
Kaixue Ma
Kiat Seng Yeo
9.1 Mixer Fundamentals
137(11)
9.1.1 Basic Mixer Operation
137(2)
9.1.2 Controlled Transconductance Mixer
139(3)
9.1.3 Transconductor Implementation
142(2)
9.1.4 The Issue of Balance in Mixers
144(4)
9.2 Fundamental Mixers
148(10)
9.2.1 FET Resistive Mixer
148(3)
9.2.2 Gilbert Cell
151(2)
9.2.3 Gilbert Cell--Based Mixer
153(1)
9.2.4 Some Techniques Used in Gilbert Cell--Based Mixers
154(4)
9.3 Sub-Harmonic Mixers
158(19)
9.3.1 LO Self-Mixing
158(1)
9.3.2 Anti-Parallel Diode Pair
159(2)
9.3.3 Techniques Used in Sub-Harmonic APDP Mixer
161(4)
9.3.4 Topology of Transistor-Based Sub-Harmonic Mixer
165(2)
9.3.5 Operation Mechanism of the Transistor-Based 2× HM
167(2)
9.3.6 A 60 GHz Transistor-Based 2× Sub-Harmonic Modulator
169(5)
9.3.7 Some Techniques Used in Sub-harmonic Mixer Designs
174(2)
9.3.8 The 4× Sub-Harmonic Mixer
176(1)
9.4 Summary
177(6)
10 Voltage-Controlled Oscillator
183(24)
Zou Qiong
Kaixue Ma
Kiat Seng Yeo
10.1 VCO Basics
184(6)
10.1.1 Overview of VCO Architectures
184(1)
10.1.2 Oscillator Theory
185(1)
10.1.3 Performance Parameter
186(4)
10.2 LC-Tank
190(5)
10.2.1 Quality Factor
191(2)
10.2.2 Tank Components
193(2)
10.3 LC-VCO Topologies for Millimeter-Wave Frequency
195(6)
10.3.1 Cross-Coupled LC-VCO
195(3)
10.3.2 Colpitts VCO
198(3)
10.4 Summary
201(6)
11 Microwave and Millimeter-Wave Switches
207(18)
Fanyi Meng
Kaixue Ma
Kiat Seng Yeo
11.1 CMOS FET Transistor
208(4)
11.2 SPDT Switches Based on λg/4 T-line Topology
212(1)
11.3 SPDT Switches Based on Magnetically Switchable Artificial Resonator Topology
213(1)
11.4 Main Coupled Lines
213(5)
11.5 Auxiliary Coupled Lines
218(3)
11.6 State-of-the-Art Switches
221(4)
12 Millimeter-Wave Beam Forming
225(20)
Fanyi Meng
Kaixue Ma
Kiat Seng Yeo
12.1 Current Tread
227(1)
12.2 Recent Implementations
227(1)
12.3 Variable Phase Shifters
228(3)
12.4 Reflective-Type Phase Shifter
231(2)
12.5 Switched-Type Phase Shifter
233(3)
12.6 Vector-Modulation Phase Shifter
236(1)
12.7 Loaded-Line Phase Shifter
237(2)
12.8 Comparison
239(6)
13 Frequency Synthesizer
245(38)
Nagarajan Mahalingam
Kaixue Ma
Kiat Seng Yeo
13.1 Introduction to Concept of Frequency Synthesis
246(1)
13.2 Phase-Locked Loop Frequency Synthesizer
247(14)
13.2.1 Performance Parameters
247(1)
13.2.1.1 Frequency tuning range
248(1)
13.2.1.2 Phase noise
248(1)
13.2.1.3 Spurious signals
249(1)
13.2.1.4 Frequency resolution and settling time
250(1)
13.2.1.5 Loop bandwidth
251(1)
13.2.1.6 Power consumption and output power
251(1)
13.2.2 Phase-Lock Loop Modeling
252(1)
13.2.2.1 Linearized PLL analysis
252(4)
13.2.2.2 PLL noise analysis
256(2)
13.2.3 Phase-Lock Loop Frequency Synthesizer Architectures
258(1)
13.2.3.1 Integer-N frequency synthesizer
258(2)
13.2.3.2 Fractional-N frequency synthesizer
260(1)
13.3 Frequency Synthesizer Building Blocks
261(22)
13.3.1 Voltage-Controlled Oscillator
261(1)
13.3.1.1 Ring oscillator
261(1)
13.3.1.2 LC oscillator
262(1)
13.3.1.3 Phase noise in oscillators
262(2)
13.3.1.4 Circuit implementation of LC oscillators
264(1)
13.3.2 High-Frequency Divider
264(1)
13.3.2.1 Static frequency divider
265(1)
13.3.2.2 Injection locked frequency divider
266(1)
13.3.2.3 Circuit implementation of ILFD
267(1)
13.3.2.4 ILFD design example
268(4)
13.3.3 Low-Frequency Divider
272(1)
13.3.4 Phase Frequency Detector
273(2)
13.3.5 Charge Pump
275(1)
13.3.5.1 Current mismatch
276(1)
13.3.5.2 Leakage current
276(1)
13.3.5.3 Clock feedthrough
277(1)
13.3.5.4 Charge sharing
277(1)
13.3.5.5 Charge injection
278(5)
14 Digital IC Design for Transceiver SOC
283(36)
Wang Yisheng
Kaixue Ma
Kiat Seng Yeo
14.1 Digital Design Flow
284(1)
14.2 Standard Library Introduction
284(7)
14.2.1 Technology File
286(1)
14.2.2 Standard Cell
286(1)
14.2.3 RAM, ROM IP Compiler
287(1)
14.2.4 IP from Third-Party Vendor
287(1)
14.2.5 Power Management Kits
288(1)
14.2.6 Library Files
289(1)
14.2.6.1 Timing and power library
289(1)
14.2.6.2 Physical definition
289(1)
14.2.6.3 Current source model
290(1)
14.2.6.4 Verilog and spice module
291(1)
14.2.6.5 Layout vs. schematic netlist
291(1)
14.3 Digital Frontend Design Flow
291(9)
14.3.1 System-Level Design
292(2)
14.3.2 HDL Coding, Simulation, and Verification
294(1)
14.3.2.1 SystemVerilog-based verification
295(1)
14.3.2.2 DesignWare IP
295(2)
14.3.2.3 Hardware-based verification
297(1)
14.3.3 Synthesis Based on Design Constraints
297(1)
14.3.4 Static Timing Analysis
298(1)
14.3.5 Formal Equivalence Checking
298(1)
14.3.6 Design for Testability
299(1)
14.4 Digital Backend Design Flow
300(8)
14.4.1 Floorplanning
300(1)
14.4.1.1 Pad ring
301(1)
14.4.1.2 Macro IP placement
302(1)
14.4.1.3 Power network
302(1)
14.4.2 Placement
303(1)
14.4.3 Clock Tree Synthesis
303(1)
14.4.4 Routing
304(1)
14.4.5 RC Extraction
305(1)
14.4.6 Multi-Mode, Multi-Corner Analysis and Optimization
306(1)
14.4.7 Signoff Static Timing Analysis
306(1)
14.4.8 Formal Verification
307(1)
14.4.9 DRC/LVS
307(1)
14.5 Low-Power IC Design Methodology
308(11)
14.5.1 Power Consumption Source
308(1)
14.5.1.1 Static power
308(2)
14.5.1.2 Dynamic power
310(1)
14.5.2 Low-Power Technologies
311(1)
14.5.2.1 Clock gating
311(1)
14.5.2.2 Logic-level power reduction
312(1)
14.5.2.3 Multiple-VT design
313(1)
14.5.2.4 Multiple-voltage design
313(1)
14.5.2.5 Power gating technology
314(1)
14.5.2.6 Unified power format
314(5)
15 60 GHz Transceiver SOC
319(14)
Kaixue Ma
Kiat Seng Yeo
15.1 60 GHz RF Transceiver SOC Architecture
321(2)
15.2 Synthesizer and the LO Feed Network
323(2)
15.3 Interface and Spurious Control
325(8)
Index 333
Kaixue Ma is a full professor in the University of Electronic Science and Technology of China (UESTC). He received his B.E. and M.E. degrees from Northwestern Polytechnical University (NWPU), China, and Ph.D from Nanyang Technological University (NTU), Singapore. From 1997 to 2002, he was with the China Academy of Space Technology (Xian), where he was Group Leader of millimeter-wave group for space-borne microwave and millimeter-wave (MMW) components and subsystems for satellite payload and very small aperture terminal (VSAT) ground station. From 2005 to 2007, he was with MEDs Technologies as an R&D manager, where he provided design services and product development. From 2007 to 2010, he was with ST Electronics as an R&D manager. From 2010 to 2013, he was a senior research fellow and team leader of radio frequencyintegrated circuit (RFIC)/MMW group researching on 60 GHz design at NTU. He is a senior member of IEEE, has filed 13 patents and authored/co-authored over 150 international top-tier refereed journal and conference papers. He received the Best Paper Award in IEEE SOCC2011, IEEK SOC Design Group Award, Chip Design Competition Bronze Award in ISIC2011, and the "Special Mention" Award under Emerging Technologies Category Awards for Singapores Next Generation WiFi Chipset in 2012 by Singapore Infocomm Technology Federation (SiTF). Prof. Ma has been honored with the National "Thousand Talent Program" Award from China.

Kiat Seng Yeo is associate provost (Graduate Studies and International Relations) at Singapore University of Technology and Design (SUTD). He received his B.Eng. and Ph.D in electrical engineering in 1993 and 1996, respectively, from NTU. He is member of board of advisors of the Singapore Semiconductor Industry Association and is a widely known authority in low-power RF/MMW IC design and a recognized expert in complementary metal-oxide semiconductor technology. Before his appointment at SUTD, he was associate chair (Research), Head of Division of Circuits and Systems, and founding director of Virtus of the School of Electrical and Electronic Engineering at NTU. He has published 6 books, 5 book chapters, over 500 international top-tier refereed journal and conference papers, and holds 35 patents. Prof. Yeo holds/has held key positions in many international conferences as advisor, general chair, co-general chair and technical Chair. He was awarded the Public Administration Medal (Bronze) on National Day 2009 by the President of the Republic of Singapore and was also awarded the distinguished Nanyang Alumni Award in 2009 for his outstanding contributions to the university and society. Prof. Yeo is an IEEE Fellow for his contributions to low-power IC design.