Recent demands for improvements in wireless transceivers has dictated designers build in lower voltages, lower power and higher frequencies. However, as voltages decrease, many existing design techniques are no longer applicable. The authors, an academician and a design practitioner, describe synthesizer fundamentals, design of building blocks, low-voltage design considerations and techniques, behavior simulation, and three model devices: a two-volt 900 MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers, a 1.5-volt 900 MHz monolithic CMOS fast-switching synthesizer for wireless applications, and a one-volt 5.2 GHz fully integrated CMOS synthesizer for WLAN IEEE 802.11a. The authors include comprehensive references. Annotation ©2004 Book News, Inc., Portland, OR (booknews.com)
Architectures and design techniques for producing modern CMOS frequency synthesizers.
This book provides architectures and design techniques to enable CMOS frequency synthesizers to operate at low-supply voltage at high frequency with good phase noise and low power consumption. It offers in-depth updates on many of these techniques, and introduces useful guidelines and step-by-step procedures on behavior simulations of frequency synthesizers. Finally, the authors feature four successful prototypes to illustrate potential applications of the architectures and design techniques described. Their work will prove useful for engineers, managers, and researchers working in RFIC design for wireless applications.
