Enabled by the development and introduction of new materials, the semiconductor industry continues to follow Moore's law into 32nm and 22nm technologies. Advanced interconnect structures require the use of porous dielectrics with further reduced k-values and even weaker mechanical properties, as well as much thinner metallization liners. In addition, the increasing resistivity of Cu at decreasing dimensions must be addressed in order to maintain the performance of continuously shrinking devices. To deal with these issues, and to maintain the reliability of the interconnects, innovations in materials, processes and architectures are needed. This book brings together researchers from around the world to exchange the latest advances in materials, processes, integration and reliability in advanced interconnects and packaging, and to discuss interconnects for emerging technologies. Papers from a joint session with Symposium F, Packaging, Chip-Package Interactions and Solder Materials Challenges, are also included and focus on 3D chip stacking and molecular electronics.
This book brings together researchers from around the world to exchange the latest advances in materials, processes, integration and reliability in advanced interconnects and packaging, and to discuss interconnects for emerging technologies. Papers from a joint session with Symposium F, Packaging, Chip-Package Interactions and Solder Materials Challenges, are also included and focus on 3D chip stacking and molecular electronics.
