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Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs 1st ed. 2016 [Kõva köide]

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  • Formaat: Hardback, 202 pages, kõrgus x laius: 235x155 mm, kaal: 4734 g, 78 Illustrations, color; XXVII, 202 p. 78 illus. in color., 1 Hardback
  • Sari: Embedded Systems
  • Ilmumisaeg: 19-Apr-2016
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319320939
  • ISBN-13: 9783319320939
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Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs 1st ed. 2016Suurem pilt
  • Formaat: Hardback, 202 pages, kõrgus x laius: 235x155 mm, kaal: 4734 g, 78 Illustrations, color; XXVII, 202 p. 78 illus. in color., 1 Hardback
  • Sari: Embedded Systems
  • Ilmumisaeg: 19-Apr-2016
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319320939
  • ISBN-13: 9783319320939
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783319320939.html
Märksõnad:
This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

Introduction.-Reconfigurable Real-Time Memory Controller Architecture.- Memory Patterns.- Cycle-AccurateSDRAM Power Modeling.- Power/Performance Trade-Offs.- Conservative Open-PagePolicy.- Reconfiguration.- Related Work.-Conclusions and Future Work.- Appendix A: ILP Problem Formation.- AppendixB: Memory Specifications.- Appendix C: Code Listings.- Appendix D: List ofAcronyms.- Appendix E: List of Symbols.
1 Introduction
1(16)
1.1 The SoC---SDRAM Interface
2(1)
1.2 SDRAM Controllers
3(1)
1.3 Cramming More Applications onto (Power-Constrained) SoCs
4(2)
1.4 Performance
6(3)
1.4.1 Application Requirements
6(1)
1.4.2 Interference
7(1)
1.4.3 Predictable Performance
7(1)
1.4.4 Composable Performance
8(1)
1.5 Requirements for SDRAM Controllers in Modern SoCs
9(1)
1.6 Problem Statement and Contributions
10(3)
1.6.1 Multi-generation Power-Aware Command Scheduling
11(1)
1.6.2 Improving Average-Case Performance Without Affecting Worst-Case Performance
12(1)
1.6.3 Reconfigurable Architecture
12(1)
1.7 Outline
13(4)
References
14(3)
2 Reconfigurable Real-Time Memory Controller Architecture
17(40)
2.1 SDRAM
18(6)
2.1.1 SDRAM Commands
19(3)
2.1.2 Timings and Timing Constraints
22(1)
2.1.3 Memory Generations
22(1)
2.1.4 Memory Hierarchies
23(1)
2.2 Pattern-Based SDRAM Controllers
24(3)
2.2.1 Burst Grouping
25(2)
2.3 Controller Architecture
27(8)
2.3.1 Resource Front-End
28(3)
2.3.2 SDRAM Back-End
31(3)
2.3.3 PHY
34(1)
2.3.4 Reconfiguration Infrastructure
34(1)
2.4 Worst-Case Performance Analysis
35(12)
2.4.1 Latency-Rate Servers
35(1)
2.4.2 Back-End Performance
36(9)
2.4.3 Front-End Performance
45(1)
2.4.4 Worst-Case Response Times
46(1)
2.5 CompSOC Controller Instance
47(2)
2.6 Evaluation
49(4)
2.6.1 Synthesis Setup
49(1)
2.6.2 Synthesis Results
50(3)
2.7 Conclusion
53(4)
References
54(3)
3 Memory Patterns
57(36)
3.1 Generalized Command Scheduling Rules
58(2)
3.2 Predictable Patterns
60(14)
3.2.1 Pattern Generation with Variable Bank Interleaving
63(4)
3.2.2 BS PBGI Heuristic for DDR4 Pattern Generation
67(2)
3.2.3 Auxiliary Patterns
69(1)
3.2.4 ILP-Based Pattern Generation
69(3)
3.2.5 Memory Map Implications
72(2)
3.3 Composable Pattern Conversion
74(4)
3.3.1 Composable Memory Pattern Generation
74(3)
3.3.2 Impact on Memory Efficiency
77(1)
3.4 Evaluation
78(11)
3.4.1 Test Memories
78(1)
3.4.2 Evaluation of Pattern-Generation Heuristics
79(3)
3.4.3 Composable Patterns
82(7)
3.5 Conclusion
89(4)
References
90(3)
4 Cycle-Accurate SDRAM Power Modeling
93(18)
4.1 High-Level Description of the DRAMPower Model
94(1)
4.2 Background on SDRAM Currents
94(2)
4.3 SDRAM Power State Machine
96(1)
4.4 Determining the Energy Cost of a Command
97(3)
4.4.1 ACT, PRE, and PREA Commands
98(1)
4.4.2 RD and WR Commands
99(1)
4.4.3 REF Commands
100(1)
4.5 Adaptation to LPDDR and WIDE I/O Memories
100(1)
4.6 Trace-Level Energy and Power Calculation in DRAMPower
101(1)
4.7 Related Work
102(3)
4.7.1 Micron's Approach
103(1)
4.7.2 Other Power Models
104(1)
4.8 Evaluation
105(3)
4.8.1 Experimental Setup
105(1)
4.8.2 Results
106(2)
4.9 Conclusion
108(3)
References
108(3)
5 Power/Performance Trade-Offs
111(14)
5.1 Worst-Case Bandwidth, Energy, and Power Metrics
111(2)
5.1.1 Calculating Worst-Case Power and Energy Efficiency
112(1)
5.2 Worst-Case Bandwidth/Power Trends
113(6)
5.2.1 Comparing Pattern Configurations of a Single Memory Device
116(1)
5.2.2 Comparing Multiple Speed Bins and SDRAM Types
117(2)
5.3 Worst-Case Response Time of an Atom
119(2)
5.4 Evaluation
121(2)
5.5 Conclusion
123(2)
References
123(2)
6 Conservative Open-Page Policy
125(20)
6.1 Conservative Open-Page Policy
126(3)
6.2 Impact on Pattern-Based Controller
129(2)
6.3 Using Explicit Precharge Commands
131(3)
6.4 Evaluation
134(10)
6.4.1 Time-Window Size
134(2)
6.4.2 Stall Time Reduction
136(8)
6.5 Conclusion
144(1)
References
144(1)
7 Reconfiguration
145(22)
7.1 Reconfiguration Options
146(2)
7.2 Performance Guarantees During a Use-Case Switch
148(1)
7.3 Delay Block/Arbiter Reconfiguration with Persistent Clients
149(1)
7.4 Reconfigurable TDM Arbiter
150(9)
7.4.1 Latency-Rate Parameters for TDM Arbiters
151(1)
7.4.2 Safe TDM Arbiter Reconfiguration protocol
152(1)
7.4.3 Arbiter Architecture
153(1)
7.4.4 Latency-Rate Guarantees During Reconfiguration
154(5)
7.5 Evaluation
159(5)
7.5.1 Predictable Performance During Reconfiguration
160(2)
7.5.2 Composable Performance During Reconfiguration
162(2)
7.6 Conclusion
164(3)
References
165(2)
8 Related Work
167(16)
8.1 SDRAM Controllers
167(11)
8.1.1 Average-Case-Oriented Controllers
167(1)
8.1.2 Real-Time-Oriented Controllers
168(10)
8.2 SDRAM Performance Overviews
178(1)
8.3 Reconfiguration
179(4)
References
180(3)
9 Conclusions and Future Work
183(6)
9.1 Conclusions
183(3)
9.2 Future Work
186(3)
References
187(2)
Appendix A ILP Problem Formulation 189(8)
Appendix B Memory Specifications 197(4)
Appendix C Code Listings 201
Sven Goossens received his M.Sc. in Embedded Systems from the Eindhoven University of Technology in 2010. He worked as a researcher in the Electrical Engineering of the same university until 2011, and then started as a Ph.D. student, graduating in 2015. He is currently employed as a Hardware Architect at Intrinsic-ID. His research interests include mixed time-criticality systems, composability and SDRAM controllers.

Karthik Chandrasekar earned his M.Sc. degree in Computer Engineering from TU Delft in the Netherlands in November 2009. In October 2014, he received his Ph.D. also from the same university. His research interests include SoC Architectures, DRAM memories & memory controllers, on-chip communication networks and performance & power modeling and analysis. He is currently employed as a Senior Architect at Nvidia. Benny Akesson received his M.Sc. degree at Lund Institute of Technology, Sweden in 2005 and a Ph.D. from Eindhoven University of Technology, the Netherlands in 2010. Since then, he has been employed as a Researcher at Eindhoven University of Technology, Czech Technical University in Prague, and CISTER/INESC TEC Research Unit in Porto. Currently, he is working as a Research Fellow at TNO-ESI. His research interests include memory controller architectures, real-time scheduling, performance modeling, and performance virtualization. He has published more than 50 peer-reviewed conference papers and journal articles, as well as two books about memory controllers for real-time embedded systems.



Kees Goossens received his Ph.D. in Computer Science from the University of Edinburgh in 1993. He worked for Philips/NXP Research from 1995 to 2010 on networks-onchips for consumer electronics, where real-time performance, predictability, and costs are major constraints. He was part-time professor at Delft University from 2007 to 2010, and is now full professor at the Eindhoven University of Technology, where his research focuses on composable (virtualized), predictable (real-time), low-power embedded systems, supporting multiple models of computation. He published 4 books, 100+ papers, and 24 patents.