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Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems 2012 ed. [Kõva köide]

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  • Formaat: Hardback, 222 pages, kõrgus x laius: 235x155 mm, kaal: 535 g, XXII, 222 p., 1 Hardback
  • Sari: Embedded Systems
  • Ilmumisaeg: 08-Sep-2011
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 144198206X
  • ISBN-13: 9781441982063
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Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems 2012 ed.Suurem pilt
  • Formaat: Hardback, 222 pages, kõrgus x laius: 235x155 mm, kaal: 535 g, XXII, 222 p., 1 Hardback
  • Sari: Embedded Systems
  • Ilmumisaeg: 08-Sep-2011
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 144198206X
  • ISBN-13: 9781441982063
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781441982063.html
Märksõnad:
Verification of real-time requirements in systems-on-chip becomes more complex as applications are integrated. This book explains the concepts of predictability and composability, and shows how to apply them to the design and analysis of a memory controller.

Verification of real-time requirements in systems-on-chip becomes more complex as more applications are integrated. Predictable and composable systems can manage the increasing complexity using formal verification and simulation. This book explains the concepts of predictability and composability and shows how to apply them to the design and analysis of a memory controller, which is a key component in any real-time system.
1 Introduction
1(28)
1.1 Trends in Embedded System Design
2(13)
1.1.1 Applications
2(2)
1.1.2 Platform-Based Design
4(3)
1.1.3 Platform Architecture
7(3)
1.1.4 Mapping
10(2)
1.1.5 Verification
12(1)
1.1.6 SDRAM and Real-Time Requirements
13(2)
1.2 Problem Statement
15(1)
1.3 Requirements
16(5)
1.3.1 Predictability
16(2)
1.3.2 Abstraction
18(1)
1.3.3 Composability
19(2)
1.3.4 Automation
21(1)
1.4 System Context
21(3)
1.5 Contributions
24(1)
1.6 Outline
25(1)
1.7 Summary
26(3)
2 Proposed Solution
29(16)
2.1 Predictability
29(7)
2.1.1 Overview of Approach
29(1)
2.1.2 Predictable SDRAM Back-End
30(4)
2.1.3 Predictable Arbitration
34(2)
2.2 Abstraction
36(2)
2.3 Composability
38(3)
2.4 Automation
41(1)
2.5 Summary
42(3)
3 SDRAM Memories and Controllers
45(18)
3.1 Introduction to SDRAM
45(4)
3.1.1 SDRAM Architecture
46(1)
3.1.2 The SDRAM Protocol
47(1)
3.1.3 Timing Constraints
48(1)
3.2 Formal Model
49(1)
3.3 Memory Efficiency
50(4)
3.3.1 Refresh Efficiency
51(1)
3.3.2 Read/Write Efficiency
51(1)
3.3.3 Bank Efficiency
52(1)
3.3.4 Command Efficiency
52(1)
3.3.5 Data Efficiency
52(1)
3.3.6 Gross and Net Efficiencies
53(1)
3.3.7 Memory Efficiency Trend
54(1)
3.4 Memory Controllers
54(6)
3.4.1 Bus and Arbiter
55(1)
3.4.2 Command Generator
56(1)
3.4.3 Memory Map
57(3)
3.5 Summary
60(3)
4 Predictable SDRAM Back-End
63(42)
4.1 Overview of Predictable SDRAM Controller
63(2)
4.1.1 Arbitration
64(1)
4.1.2 Command Generator
64(1)
4.1.3 Memory Map
65(1)
4.2 Memory Patterns
65(5)
4.2.1 Scheduling Rules
66(1)
4.2.2 Pattern Descriptions
66(2)
4.2.3 Pattern Set Dominance
68(2)
4.3 Memory Efficiency Bound
70(5)
4.3.1 Refresh Efficiency
70(2)
4.3.2 Read/Write Efficiency
72(1)
4.3.3 Bank and Command Efficiency
72(1)
4.3.4 Data Efficiency
73(2)
4.4 Latency Bound
75(2)
4.5 Memory Pattern Generation
77(12)
4.5.1 Design Decisions
78(3)
4.5.2 Access Pattern Termination
81(1)
4.5.3 Branch and Bound
82(3)
4.5.4 As-Soon-As-Possible Scheduling
85(2)
4.5.5 Bank Scheduling
87(1)
4.5.6 Computing Auxiliary Patterns
88(1)
4.6 Architecture and Synthesis
89(1)
4.7 Experimental Results
90(11)
4.7.1 Experimental Setup
91(1)
4.7.2 Algorithm Evaluation
91(8)
4.7.3 Bounding Net Bandwidth
99(1)
4.7.4 Tightness of Net Bandwidth Bound
100(1)
4.8 Summary
101(4)
5 Resource Arbitration
105(38)
5.1 Arbiter Requirements
106(1)
5.2 Formal Model
106(6)
5.2.1 Requested Service Model
106(2)
5.2.2 Provided Service Model
108(4)
5.3 Latency-Rate Servers
112(2)
5.4 Time-Division Multiplexing
114(5)
5.4.1 Overview
115(1)
5.4.2 Analysis
116(3)
5.5 Frame-Based Static-Priority Arbitration
119(2)
5.5.1 Overview
119(1)
5.5.2 Analysis
119(2)
5.6 Credit-Controlled Static-Priority Arbitration
121(5)
5.6.1 Overview
121(1)
5.6.2 Active Period Rate Regulation
122(3)
5.6.3 Analysis
125(1)
5.7 Experimental Results
126(15)
5.7.1 Experimental Setup
127(1)
5.7.2 Evaluation of Service Guarantee
127(2)
5.7.3 Latency Distributions
129(6)
5.7.4 Tightness of Service Latency Bound
135(3)
5.7.5 Allocation Properties
138(3)
5.8 Summary
141(2)
6 Composable Resource Front-End
143(28)
6.1 Overview of Approach
144(2)
6.2 Formal Model
146(3)
6.3 Architecture
149(9)
6.3.1 Architecture Overview
149(1)
6.3.2 Atomizer
150(1)
6.3.3 Delay Block
150(4)
6.3.4 Data Bus
154(1)
6.3.5 Synthesis Results
155(3)
6.4 Experiments
158(10)
6.4.1 SRAM Experiments
158(7)
6.4.2 SDRAM Experiments
165(3)
6.5 Summary
168(3)
7 Configuration
171(16)
7.1 Formal Model
171(2)
7.2 Memory Pattern Generation
173(2)
7.3 Normalization of Requirements
175(2)
7.4 Arbiter Configuration
177(4)
7.4.1 Bandwidth Allocation
178(2)
7.4.2 Priority Assignment
180(1)
7.5 Denormalization of Allocation
181(1)
7.6 Requirement Verification
182(2)
7.7 Experimental Results
184(2)
7.8 Summary
186(1)
8 Related Work
187(8)
8.1 Resource Arbitration
187(2)
8.2 SDRAM Controllers
189(3)
8.3 Composable Service
192(3)
9 Conclusions and Future Work
195(8)
9.1 Conclusions
195(3)
9.1.1 Predictability
196(1)
9.1.2 Abstraction
196(1)
9.1.3 Composability
197(1)
9.1.4 Automation
197(1)
9.2 Future Work
198(5)
9.2.1 Reducing Power Consumption
198(1)
9.2.2 Opportunities with 3D Integration
198(1)
9.2.3 Improved Arbiter Configuration
199(1)
9.2.4 Reconfiguration
200(1)
9.2.5 Data-Flow Model of Memory Controller
200(3)
A System XML Specification
203(4)
A.1 Architecture Specification
203(2)
A.2 Use-Case Specification
205(2)
B Glossary
207(4)
B.1 List of Abbreviations
207(1)
B.2 List of Symbols
208(3)
References 211(8)
Index 219