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Micro-Relay Technology for Energy-Efficient Integrated Circuits 2015 ed. [Kõva köide]

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  • Formaat: Hardback, 183 pages, kõrgus x laius: 235x155 mm, kaal: 4558 g, 56 Illustrations, color; 111 Illustrations, black and white; X, 183 p. 167 illus., 56 illus. in color., 1 Hardback
  • Sari: Microsystems and Nanosystems
  • Ilmumisaeg: 20-Oct-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1493921274
  • ISBN-13: 9781493921270
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Micro-Relay Technology for Energy-Efficient Integrated Circuits 2015 ed.Suurem pilt
  • Formaat: Hardback, 183 pages, kõrgus x laius: 235x155 mm, kaal: 4558 g, 56 Illustrations, color; 111 Illustrations, black and white; X, 183 p. 167 illus., 56 illus. in color., 1 Hardback
  • Sari: Microsystems and Nanosystems
  • Ilmumisaeg: 20-Oct-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1493921274
  • ISBN-13: 9781493921270
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781493921270.html
Märksõnad:
This volume describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers, and highlights the importance of co-design across design hierarchies when trying to optimize system performance (in this case, energy-efficiency). The book will also appeal to researchers and engineers focused on semiconductor, integrated circuits, and energy efficient electronics.
1 A New Era of Old Electronics
1(12)
1.1 Introduction
1(1)
1.2 The Call for Energy-Efficiency
2(1)
1.3 Energy-Efficiency Limitations of CMOS
3(4)
1.3.1 CMOS Scaling
3(2)
1.3.2 Minimizing CMOS Energy Consumption
5(2)
1.3.3 Temporarily Averting the CMOS Power Crisis
7(1)
1.4 Micro-relays as an Energy-Efficient Technology
7(2)
1.4.1 Electromechanical Devices
8(1)
1.4.2 Energy Outlook for Micro-relays
9(1)
1.5 Book Summary
9(4)
References
10(3)
2 Design and Modeling of Micro-relay
13(34)
2.1 Introduction
13(1)
2.2 Relay Structure and Operation
13(3)
2.3 Design and Modeling of Mechanical Beams
16(17)
2.3.1 Mechanical Modeling of Cantilever Beams
20(3)
2.3.2 Mechanical Modeling of Fixed-fixed Beams
23(2)
2.3.3 Impact of Stress Gradient and Residual Stress
25(7)
2.3.4 Stress/Strain Gradient Free Beam Design
32(1)
2.4 Design and Modeling of Torsional Beam
33(4)
2.5 Dimple Support Design
37(1)
2.6 Contact Resistance
38(1)
2.7 Dynamic Behavior of Micro-relays
39(5)
2.7.1 Effective Mass Model
41(2)
2.7.2 Damping Physics
43(1)
2.8 Relay Energy Consumption per Operation
44(3)
Appendix: Spring Constant of a Pinned-Pinned Beam
44(2)
References
46(1)
3 Micro-relay Technologies
47(22)
3.1 Introduction
47(1)
3.2 Process Integration Considerations for Micro-relay Technology
47(2)
3.3 Berkeley Folded-Flexure Relay with Poly-Si0.4Ges Structure and Tungsten Contacts
49(6)
3.3.1 Static Performance
49(6)
3.3.2 Dynamic Performance53
3.4 KAIST Titanium-Nitride Relay Technology
55(2)
3.5 Stanford Laterally Actuated Platinum-Coated Polysilicon Relay
57(2)
3.6 Sandia National Laboratories Laterally Actuated Ruthenium Relay
59(2)
3.7 Integrations with CMOS
61(2)
3.8 University of Pennsylvania Piezoelectric Aluminum Nitride Micro-relay
63(6)
References
68(1)
4 Micro-relay Reliability
69(12)
4.1 Introduction
69(1)
4.2 Structural Fatigue
69(1)
4.3 Dielectric Charging
70(2)
4.4 Contact Surface Oxidation
72(2)
4.5 Contact Welding
74(7)
4.5.1 Contact Endurance Model
74(2)
4.5.2 Validation of the Contact Endurance Model
76(2)
4.5.3 Design Implications
78(2)
References
80(1)
5 Optimization and Scaling of Micro-relays for Ultralow-Power Digital Logic
81(22)
5.1 Introduction
81(1)
5.2 Relay Energy-Delay Optimization
82(6)
5.2.1 Sensitivity Analysis
84(1)
5.2.2 Sensitivity to Supply Voltage (Vdd)
85(1)
5.2.3 Sensitivity to Actuation Area (A)
86(1)
5.2.4 Sensitivity to As-Fabricated Gap Thickness (g)
87(1)
5.2.5 Sensitivity to Beam Length (L)
87(1)
5.3 Relay Design Optimization
88(8)
5.3.1 Optimal Gap Thickness Ratio (gd/g)
89(1)
5.3.2 Optimal Vdd/Vpi
90(1)
5.3.3 Optimal Actuation Area (A) and Supply Voltage (Vdd)
91(1)
5.3.4 Optimal Beam Length (L)
92(1)
5.3.5 Relay Design Optimization Procedure
93(3)
5.3.6 Energy-Efficiency Limit
96(1)
5.4 Scaling Implications
96(7)
References
100(3)
6 Integrated Circuit Design with Micro-relays
103(34)
6.1 Introduction
103(1)
6.2 Micro-relay Switching Characteristics
104(2)
6.2.1 DC Switching Characteristics of Micro-relays
104(1)
6.2.2 Dynamic Switching Characteristics of Micro-relays
105(1)
6.3 Micro-relays as a Circuit Building Block
106(5)
6.3.1 Micro-relays as a Digital Logic Element
106(1)
6.3.2 Micro-relays as an Analog Processing Element
107(1)
6.3.3 Secondary Effects in Micro-relays
108(3)
6.4 Circuit Modeling for Micro-relays
111(5)
6.4.1 The Device Model
111(1)
6.4.2 Model Extensions for Simulation
112(2)
6.4.3 Model Convergence
114(2)
6.5 The Static Micro-relay Inverter (Buffer)
116(7)
6.5.1 Micro-relay Inverter Operation
116(1)
6.5.2 Static Behavior and Robustness of a Micro-relay Inverter
117(3)
6.5.3 Dynamic Switching Behavior of a Micro-relay Inverter
120(3)
6.6 Combinational Logic Design with Micro-relays
123(5)
6.6.1 Logic Styles for MEM Relays
124(2)
6.6.2 Pass-Transistor Logic Design with Micro-relays
126(2)
6.7 Summary
128(9)
Appendix: Micro-relay Verilog-A Model
128(6)
References
134(3)
7 Micro-relay Circuits for VLSI Applications
137(44)
7.1 Introduction
137(1)
7.2 Arithmetic Building Blocks
137(14)
7.2.1 Micro-relay Adder Design and Performance
138(3)
7.2.2 Micro-relay Multiplier Design and Performance
141(9)
7.2.3 Relay Shifters
150(1)
7.3 Sequential Relay Circuits and Memory
151(7)
7.3.1 Static Latches and Flip-flops
151(2)
7.3.2 Dynamic Latches and Registers
153(1)
7.3.3 Pipelined Datapath Timing
154(2)
7.3.4 Relay Memory Circuits
156(2)
7.4 Synthesis of Relay Logic
158(6)
7.4.1 Tree-Based Relay Synthesis
158(1)
7.4.2 Relay Synthesis with Binary Decision Diagrams (BDD)
159(5)
7.5 Mixed-Signal Relay Circuits
164(13)
7.5.1 Clocking Generation
164(2)
7.5.2 A Micro-relay Digital-to-Analog Converter (DAC)
166(2)
7.5.3 Sub-mechanical Delay Data Transmission
168(2)
7.5.4 A Micro-relay Analog-to-Digital Converter (ADC)
170(5)
7.5.5 Sub-mechanical Bit Time Data Receiver
175(2)
7.6 Summary
177(4)
References
177(4)
Index 181
Fred Chen currently works at Lion Semiconductor, Inc. Hei Kam currently works at Intel Corporation and was formerly a graduate student at UC Berkeley.