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Microelectronic Circuit Design 5th edition [Pehme köide]

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  • Formaat: Paperback / softback, 1376 pages, kõrgus x laius x paksus: 252x201x43 mm, kaal: 2012 g
  • Ilmumisaeg: 16-Mar-2015
  • Kirjastus: McGraw-Hill Education
  • ISBN-10: 1259252450
  • ISBN-13: 9781259252457
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Microelectronic Circuit Design 5th editionSuurem pilt
  • Formaat: Paperback / softback, 1376 pages, kõrgus x laius x paksus: 252x201x43 mm, kaal: 2012 g
  • Ilmumisaeg: 16-Mar-2015
  • Kirjastus: McGraw-Hill Education
  • ISBN-10: 1259252450
  • ISBN-13: 9781259252457
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781259252457.html
Märksõnad:
Richard Jaeger and Travis Blalock present a balanced coverage of analog and digital circuits; students will develop a comprehensive understanding of the basic techniques of modern electronic circuit design, analog and digital, discrete and integrated.A broad spectrum of topics are included in Microelectronic Circuit Design which gives the professor the option to easily select and customize the material to satisfy a two-semester or three-quarter sequence in electronics. Jaeger/Blalock emphasizes design through the use of design examples and design notes. Excellent pedagogical elements include chapter opening vignettes, chapter objectives, Electronics in Action boxes, a problem-solving methodology, and "Design Note boxes.

The use of the well-defined problem-solving methodology presented in this text can significantly enhance an engineers ability to understand the issues related to design. The design examples assist in building and understanding the design process.
Preface xx
Chapter-by-Chapter Summary xxv
Part One Solid-State Electronics And Devices 1(280)
Chapter 1 Introduction To Electronics
3(38)
1.1 A Brief History of Electronics: From Vacuum Tubes to Giga-Scale Integration
5(3)
1.2 Classification of Electronic Signals
8(4)
1.2.1 Digital Signals
9(1)
1.2.2 Analog Signals
9(1)
1.2.3 A/D and D/A Converters-Bridging the Analog and Digital Domains
10(2)
1.3 Notational Conventions
12(1)
1.4 Problem-Solving Approach
13(2)
1.5 Important Concepts from Circuit Theory
15(6)
1.5.1 Voltage and Current Division
15(1)
1.5.2 Thevenin and Norton Circuit Representations
16(5)
1.6 Frequency Spectrum of Electronic Signals
21(1)
1.7 Amplifiers
22(4)
1.7.1 Ideal Operational Amplifiers
23(2)
1.7.2 Amplifier Frequency Response
25(1)
1.8 Element Variations in Circuit Design
26(8)
1.8.1 Mathematical Modeling of Tolerances
26(1)
1.8.2 Worst-Case Analysis
27(2)
1.8.3 Monte Carlo Analysis
29(3)
1.8.4 Temperature Coefficients
32(2)
1.9 Numeric Precision
34(1)
Summary
34(1)
Key Terms
35(1)
References
36(1)
Additional Reading
36(1)
Problems
36(5)
Chapter 2 Solid-State Electronics
41(31)
2.1 Solid-State Electronic Materials
43(1)
2.2 Covalent Bond Model
44(3)
2.3 Drift Currents and Mobility in Semiconductors
47(2)
2.3.1 Drift Currents
47(1)
2.3.2 Mobility
48(1)
2.3.3 Velocity Saturation
48(1)
2.4 Resistivity of Intrinsic Silicon
49(1)
2.5 Impurities in Semiconductors
50(1)
2.5.1 Donor Impurities in Silicon
51(1)
2.5.2 Acceptor Impurities in Silicon
51(1)
2.6 Electron and Hole Concentrations in Doped Semiconductors
51(3)
2.6.1 n-Type Material (ND > NA)
52(1)
2.6.2 p-Type Material (NA > ND)
53(1)
2.7 Mobility and Resistivity in Doped Semiconductors
54(4)
2.8 Diffusion Currents
58(1)
2.9 Total Current
59(1)
2.10 Energy Band Model
60(3)
2.10.1 Electron-Hole Pair Generation in an Intrinsic Semiconductor
60(1)
2.10.2 Energy Band Model for a Doped Semiconductor
61(1)
2.10.3 Compensated Semiconductors
61(2)
2.11 Overview of Integrated Circuit Fabrication
63(3)
Summary
66(1)
Key Terms
67(1)
Reference
68(1)
Additional Reading
68(1)
Problems
68(4)
Chapter 3 Solid-State Diodes And Diode Circuits
72(72)
3.1 The pn Junction Diode
73(5)
3.1.1 pn Junction Electrostatics
73(4)
3.1.2 Internal Diode Currents
77(1)
3.2 The i-v Characteristics of the Diode
78(2)
3.3 The Diode Equation: A Mathematical Model for the Diode
80(3)
3.4 Diode Characteristics under Reverse, Zero, and Forward Bias
83(3)
3.4.1 Reverse Bias
83(1)
3.4.2 Zero Bias
83(1)
3.4.3 Forward Bias
84(2)
3.5 Diode Temperature Coefficient
86(1)
3.6 Diodes under Reverse Bias
86(4)
3.6.1 Saturation Current in Real Diodes
87(2)
3.6.2 Reverse Breakdown
89(1)
3.6.3 Diode Model for the Breakdown Region
90(1)
3.7 pn Junction Capacitance
90(3)
3.7.1 Reverse Bias
90(1)
3.7.2 Forward Bias
91(2)
3.8 Schottky Barrier Diode
93(1)
3.9 Diode SPICE Model and Layout
93(2)
3.9.1 Diode Layout
94(1)
3.10 Diode Circuit Analysis
95(10)
3.10.1 Load-Line Analysis
96(1)
3.10.2 Analysis Using the Mathematical Model for the Diode
97(4)
3.10.3 The Ideal Diode Model
101(2)
3.10.4 Constant Voltage Drop Model
103(1)
3.10.5 Model Comparison and Discussion
104(1)
3.11 Multiple-Diode Circuits
105(3)
3.12 Analysis of Diodes Operating in the Breakdown Region
108(4)
3.12.1 Load-Line Analysis
108(1)
3.12.2 Analysis with the Piecewise Linear Model
108(1)
3.12.3 Voltage Regulation
109(1)
3.12.4 Analysis Including Zener Resistance
110(1)
3.12.5 Line and Load Regulation
111(1)
3.13 Half-Wave Rectifier Circuits
112(10)
3.13.1 Half-Wave Rectifier with Resistor Load
112(1)
3.13.2 Rectifier Filter Capacitor
113(1)
3.13.3 Half-Wave Rectifier with RC Load
114(1)
3.13.4 Ripple Voltage and Conduction Interval
115(2)
3.13.5 Diode Current
117(2)
3.13.6 Surge Current
119(1)
3.13.7 Peak-Inverse-Voltage (PIV) Rating
119(1)
3.13.8 Diode Power Dissipation
119(1)
3.13.9 Half-Wave Rectifier with Negative Output Voltage
120(2)
3.14 Full-Wave Rectifier Circuits
122(1)
3.14.1 Full-Wave Rectifier with Negative Output Voltage
123(1)
3.15 Full-Wave Bridge Rectification
123(1)
3.16 Rectifier Comparison and Design Tradeoffs
124(4)
3.17 Dynamic Switching Behavior of the Diode
128(1)
3.18 Photo Diodes, Solar Cells, and Light-Emitting Diodes
129(3)
3.18.1 Photo Diodes and Photodetectors
129(1)
3.18.2 Power Generation from Solar Cells
130(1)
3.18.3 Light-Emitting Diodes (LEDs)
131(1)
Summary
132(1)
Key Terms
133(1)
Reference
134(1)
Additional Reading
134(1)
Problems
134(10)
Chapter 4 Field-Effect Transistors
144(71)
4.1 Characteristics of the MOS Capacitor
145(2)
4.1.1 Accumulation Region
146(1)
4.1.2 Depletion Region
147(1)
4.1.3 Inversion Region
147(1)
4.2 The NMOS Transistor
147(13)
4.2.1 Qualitative i-v Behavior of the NMOS Transistor
148(1)
4.2.2 Triode Region Characteristics of the NMOS Transistor
149(3)
4.2.3 On Resistance
152(1)
4.2.4 Transconductance
153(1)
4.2.5 Saturation of the i-v Characteristics
154(1)
4.2.6 Mathematical Model in the Saturation (Pinch-Off) Region
155(1)
4.2.7 Transconductance in Saturation
156(1)
4.2.8 Channel-Length Modulation
156(1)
4.2.9 Transfer Characteristics and Depletion-Mode MOSFETs
157(2)
4.2.10 Body Effect or Substrate Sensitivity
159(1)
4.3 PMOS Transistors
160(2)
4.4 MOSFET Circuit Symbols
162(3)
4.5 Capacitances in MOS Transistors
165(2)
4.5.1 NMOS Transistor Capacitances in the Triode Region
165(1)
4.5.2 Capacitances in the Saturation Region
166(1)
4.5.3 Capacitances in Cutoff
166(1)
4.6 MOSFET Modeling in SPICE
167(1)
4.7 MOS Transistor Scaling
168(6)
4.7.1 Drain Current
169(1)
4.7.2 Gate Capacitance
169(1)
4.7.3 Circuit and Power Densities
169(1)
4.7.4 Power-Delay Product
170(1)
4.7.5 Cutoff Frequency
170(1)
4.7.6 High Field Limitations
171(1)
4.7.7 The Unified MOS Transistor Model Including High Field Limitations
172(1)
4.7.8 Subthreshold Conduction
173(1)
4.8 MOS Transistor Fabrication and Layout Design Rules
174(4)
4.8.1 Minimum Feature Size and Alignment Tolerance
174(1)
4.8.2 MOS Transistor Layout
174(4)
4.9 Biasing the NMOS Field-Effect Transistor
178(10)
4.9.1 Why Do We Need Bias?
178(2)
4.9.2 Four-Resistor Biasing
180(4)
4.9.3 Constant Gate-Source Voltage Bias
184(1)
4.9.4 Graphical Analysis for the Q-Point
184(1)
4.9.5 Analysis Including Body Effect
184(3)
4.9.6 Analysis Using the Unified Model
187(1)
4.10 Biasing the PMOS Field-Effect Transistor
188(2)
4.11 The Junction Field-Effect Transistor (JFET)
190(6)
4.11.1 The JFET with Bias Applied
191(2)
4.11.2 JFET Channel with Drain-Source Bias
193(1)
4.11.3 n-Channel JFET i-v Characteristics
193(2)
4.11.4 The p-Channel JFET
195(1)
4.11.5 Circuit Symbols and JFET Model Summary
195(1)
4.11.6 JFET Capacitances
196(1)
4.12 JFET Modeling in Spice
196(1)
4.13 Biasing the JFET and Depletion-Mode MOSFET
197(3)
Summary
200(2)
Key Terms
202(1)
References
202(1)
Problems
203(12)
Chapter 5 Bipolar Junction Transistors
215(66)
5.1 Physical Structure of the Bipolar Transistor
216(1)
5.2 The Transport Model for the npn Transistor
217(6)
5.2.1 Forward Characteristics
218(2)
5.2.2 Reverse Characteristics
220(1)
5.2.3 The Complete Transport Model Equations for Arbitrary Bias Conditions
221(2)
5.3 The pnp Transistor
223(2)
5.4 Equivalent Circuit Representations for the Transport Models
225(1)
5.5 The i-v Characteristics of the Bipolar Transistor
226(1)
5.5.1 Output Characteristics
226(1)
5.5.2 Transfer Characteristics
227(1)
5.6 The Operating Regions of the Bipolar Transistor
227(1)
5.7 Transport Model Simplifications
228(15)
5.7.1 Simplified Model for the Cutoff Region
229(2)
5.7.2 Model Simplifications for the Forward-Active Region
231(6)
5.7.3 Diodes in Bipolar Integrated Circuits
237(1)
5.7.4 Simplified Model for the Reverse-Active Region
238(2)
5.7.5 Modeling Operation in the Saturation Region
240(3)
5.8 Non ideal Behavior of the Bipolar Transistor
243(7)
5.8.1 Junction Breakdown Voltages
244(1)
5.8.2 Minority-Carrier Transport in the Base Region
244(1)
5.8.3 Base Transit Time
245(2)
5.8.4 Diffusion Capacitance
247(1)
5.8.5 Frequency Dependence of the Common-Emitter Current Gain
248(1)
5.8.6 The Early Effect and Early Voltage
248(1)
5.8.7 Modeling the Early Effect
249(1)
5.8.8 Origin of the Early Effect
249(1)
5.9 Transconductance
250(1)
5.10 Bipolar Technology and SPICE Model
251(3)
5.10.1 Qualitative Description
251(1)
5.10.2 SPICE Model Equations
252(1)
5.10.3 High-Performance Bipolar Transistors
253(1)
5.11 Practical Bias Circuits for the BJT
254(8)
5.11.1 Four-Resistor Bias Network
256(2)
5.11.2 Design Objectives for the Four-Resistor Bias Network
258(4)
5.11.3 Iterative Analysis of the Four-Resistor Bias Circuit
262(1)
5.12 Tolerances in Bias Circuits
262(6)
5.12.1 Worst-Case Analysis
263(2)
5.12.2 Monte Carlo Analysis
265(3)
Summary
268(2)
Key Terms
270(1)
References
270(1)
Problems
271(10)
Part Two Digital Electronics 281(234)
Chapter 6 Introduction To Digital Electronics
283(76)
6.1 Ideal Logic Gates
285(1)
6.2 Logic Level Definitions and Noise Margins
285(4)
6.2.1 Logic Voltage Levels
287(1)
6.2.2 Noise Margins
287(1)
6.2.3 Logic Gate Design Goals
288(1)
6.3 Dynamic Response of Logic Gates
289(2)
6.3.1 Rise Time and Fall Time
289(1)
6.3.2 Propagation Delay
290(1)
6.3.3 Power-Delay Product
290(1)
6.4 Review of Boolean Algebra
291(2)
6.5 NMOS Logic Design
293(9)
6.5.1 NMOS Inverter with Resistive Load
294(1)
6.5.2 Design of the W/L Ratio of Ms
295(1)
6.5.3 Load Resistor Design
296(1)
6.5.4 Load-Line Visualization
296(2)
6.5.5 On-Resistance of the Switching Device
298(1)
6.5.6 Noise Margin Analysis
299(1)
6.5.7 Calculation of VIL and VOH
299(1)
6.5.8 Calculation of VIH and VOL
300(1)
6.5.9 Resistor Load Inverter Noise Margins
300(1)
6.5.10 Load Resistor Problems
301(1)
6.6 Transistor Alternatives to the Load Resistor
302(13)
6.6.1 The NMOS Saturated Load Inverter
303(8)
6.6.2 NMOS Inverter with a Linear Load Device
311(1)
6.6.3 NMOS Inverter with a Depletion-Mode Load
312(3)
6.7 NMOS Inverter Summary and Comparison
315(1)
6.8 Impact of Velocity Saturation on Static Inverter Design
316(1)
6.8.1 Switching Transistor Design
316(1)
6.8.2 Load Transistor Design
316(1)
6.8.3 Velocity Saturation Impact Summary
317(1)
6.9 NMOS NAND and NOR Gates
317(4)
6.9.1 NOR Gates
318(1)
6.9.2 NAND Gates
319(1)
6.9.3 NOR and NAND Gate Layouts in NMOS Depletion-Mode Technology
320(1)
6.10 Complex NMOS Logic Design
321(5)
6.11 Power Dissipation
326(3)
6.11.1 Static Power Dissipation
326(1)
6.11.2 Dynamic Power Dissipation
327(1)
6.11.3 Power Scaling in MOS Logic Gates
328(1)
6.12 Dynamic Behavior of MOS Logic Gates
329(12)
6.12.1 Capacitances in Logic Circuits
330(1)
6.12.2 Dynamic Response of the NMOS Inverter with a Resistive Load
331(5)
6.12.3 Comparison of NMOS Inverter Delays
336(1)
6.12.4 Impact of Velocity Saturation on Inverter Delays
337(1)
6.12.5 Scaling Based upon Reference Circuit Simulation
337(1)
6.12.6 Ring Oscillator Measurement of Intrinsic Gate Delay
338(1)
6.12.7 Unloaded Inverter Delay
338(3)
6.13 PMOS Logic
341(3)
6.13.1 PMOS Inverters
341(2)
6.13.2 NOR and NAND Gates
343(1)
Summary
344(2)
Key Terms
346(1)
References
347(1)
Additional Reading
347(1)
Problems
347(12)
Chapter 7 Complementary MOS (CMOS) Logic Design
359(55)
7.1 CMOS Inverter Technology
360(2)
7.1.1 CMOS Inverter Layout
362(1)
7.2 Static Characteristics of the CMOS Inverter
362(5)
7.2.1 CMOS Voltage Transfer Characteristics
363(2)
7.2.2 Noise Margins for the CMOS Inverter
365(2)
7.3 Dynamic Behavior of the CMOS Inverter
367(6)
7.3.1 Propagation Delay Estimate
367(2)
7.3.2 Rise and Fall Times
369(1)
7.3.3 Performance Scaling
369(2)
7.3.4 Impact of Velocity Saturation on CMOS Inverter Delays
371(1)
7.3.5 Delay of Cascaded Inverters
372(1)
7.4 Power Dissipation and Power Delay Product in CMOS
373(4)
7.4.1 Static Power Dissipation
373(1)
7.4.2 Dynamic Power Dissipation
374(1)
7.4.3 Power-Delay Product
375(2)
7.5 CMOS NOR and NAND Gates
377(4)
7.5.1 CMOS NOR Gate
377(3)
7.5.2 CMOS NAND Gates
380(1)
7.6 Design of Complex Gates in CMOS
381(6)
7.7 Minimum Size Gate Design and Performance
387(2)
7.8 Cascade Buffers
389(3)
7.8.1 Cascade Buffer Delay Model
389(1)
7.8.2 Optimum Number of Stages
390(2)
7.9 The CMOS Transmission Gate
392(1)
7.10 Bistable Circuits
393(4)
7.10.1 The Bistable Latch
393(3)
7.10.2 RS Flip-Flop
396(1)
7.10.3 The D-Latch Using Transmission Gates
397(1)
7.10.4 A Master-Slave D Flip-Flop
397(1)
7.11 CMOS Latchup
397(5)
Summary
402(1)
Key Terms
403(1)
References
404(1)
Problems
404(10)
Chapter 8 MOS Memory Circuits
414(41)
8.1 Random-Access Memory (RAM)
415(2)
8.1.1 Random-Access Memory (RAM) Architecture
415(1)
8.1.2 A 256-Mb Memory Chip
416(1)
8.2 Static Memory Cells
417(7)
8.2.1 Memory Cell Isolation and Access-the 6-T Cell
417(1)
8.2.2 The Read Operation
418(4)
8.2.3 Writing Data into the 6-T Cell
422(2)
8.3 Dynamic Memory Cells
424(6)
8.3.1 The One-Transistor Cell
425(1)
8.3.2 Data Storage in the 1-T Cell
425(2)
8.3.3 Reading Data from the 1-T Cell
427(1)
8.3.4 The Four-Transistor Cell
428(2)
8.4 Sense Amplifiers
430(6)
8.4.1 A Sense Amplifier for the 6-T Cell
430(2)
8.4.2 A Sense Amplifier for the 1-T Cell
432(1)
8.4.3 The Boosted Wordline Circuit
433(1)
8.4.4 Clocked CMOS Sense Amplifiers
434(2)
8.5 Address Decoders
436(3)
8.5.1 NOR Decoder
436(1)
8.5.2 NAND Decoder
436(2)
8.5.3 Pass-Transistor Column Decoder
438(1)
8.6 Read-Only Memory (ROM)
439(3)
8.7 Flash Memory
442(5)
8.7.1 Floating Gate Technology
442(3)
8.7.2 NOR Circuit Implementations
445(1)
8.7.3 NAND Implementations
445(2)
Summary
447(1)
Key Terms
448(1)
References
449(1)
Problems
449(6)
Chapter 9 Bipolar Logic Circuits
455(60)
9.1 The Current Switch (Emitter-Coupled Pair)
456(3)
9.1.1 Mathematical Model for Static Behavior of the Current Switch
456(2)
9.1.2 Current Switch Analysis for VI > VREF
458(1)
9.1.3 Current Switch Analysis for VI < VREF
459(1)
9.2 The Emitter-Coupled Logic (ECL) Gate
459(3)
9.2.1 ECL Gate with VI = VH
460(1)
9.2.2 ECL Gate with VI = VL
461(1)
9.2.3 Input Current of the ECL Gate
461(1)
9.2.4 ECL Summary
461(1)
9.3 Noise Margin Analysis for the ECL Gate
462(2)
9.3.1 VIL, VOH, VIH, and VOL
462(1)
9.3.2 Noise Margins
463(1)
9.4 Current Source Implementation
464(2)
9.5 The ECL OR-NOR Gate
466(2)
9.6 The Emitter Follower
468(3)
9.6.1 Emitter Follower with a Load Resistor
469(2)
9.7 "Emitter Dotting" or "Wired-OR" Logic
471(1)
9.7.1 Parallel Connection of Emitter-Follower Outputs
472(1)
9.7.2 The Wired-OR Logic Function
472(1)
9.8 ECL Power-Delay Characteristics
472(4)
9.8.1 Power Dissipation
472(2)
9.8.2 Gate Delay
474(1)
9.8.3 Power-Delay Product
475(1)
9.9 Positive ECL (PECL)
476(1)
9.10 Current Mode Logic
476(7)
9.10.1 CML Logic Gates
477(1)
9.10.2 CML Logic Levels
478(1)
9.10.3 VEE Supply Voltage
478(1)
9.10.4 Higher-Level CML
479(1)
9.10.5 CML Power Reduction
480(1)
9.10.6 Source-Coupled Fet Logic (SCFL)
480(3)
9.11 The Saturating Bipolar Inverter
483(7)
9.11.1 Static Inverter Characteristics
483(1)
9.11.2 Saturation Voltage of the Bipolar Transistor
484(2)
9.11.3 Load-Line Visualization
486(1)
9.11.4 Switching Characteristics of the Saturated BJT
487(3)
9.12 A Transistor-Transistor Logic (TTL)
490(4)
9.12.1 TTL Inverter Analysis for VI = VL
490(2)
9.12.2 Analysis for VI = VH
492(1)
9.12.3 Power Consumption
493(1)
9.12.4 TTL Propagation Delay and Power-Delay Product
493(1)
9.12.5 TTL Voltage Transfer Characteristic and Noise Margins
494(1)
9.12.6 Fanout Limitations of Standard TTL
494(1)
9.13 Logic Functions in TTL
494(3)
9.13.1 Multi-Emitter Input Transistors
495(1)
9.13.2 TTL NAND Gates
495(1)
9.13.3 Input Clamping Diodes
496(1)
9.14 Schottky-Clamped TTL
497(1)
9.15 Comparison of the Power-Delay Products of ECL and TTL
498(1)
9.16 BiCMOS Logic
498(5)
9.16.1 BiCMOS Buffers
499(2)
9.16.2 BiNMOS Inverters
501(1)
9.16.3 BiCMOS Logic Gates
502(1)
Summary
503(1)
Key Terms
504(1)
References
505(1)
Additional Reading
505(1)
Problems
505(10)
Part Three Analog Electronics 515(776)
Chapter 10 Analog Systems And Ideal Operational Amplifiers
517(70)
10.1 An Example of an Analog Electronic System
518(1)
10.2 Amplification
519(6)
10.2.1 Voltage Gain
520(1)
10.2.2 Current Gain
521(1)
10.2.3 Power Gain
521(1)
10.2.4 The Decibel Scale
522(3)
10.3 Two-Port Models for Amplifiers
525(4)
10.3.1 The g-Parameters
525(4)
10.4 Mismatched Source and Load Resistances
529(3)
10.5 Introduction to Operational Amplifiers
532(4)
10.5.1 The Differential Amplifier
532(1)
10.5.2 Differential Amplifier Voltage Transfer Characteristic
533(1)
10.5.3 Voltage Gain
533(3)
10.6 Distortion in Amplifiers
536(1)
10.7 Differential Amplifier Model
537(2)
10.8 Ideal Differential and Operational Amplifiers
539(1)
10.8.1 Assumptions for Ideal Operational Amplifier Analysis
539(1)
10.9 Analysis of Circuits Containing Ideal Operational Amplifiers
540(15)
10.9.1 The Inverting Amplifier
541(3)
10.9.2 The Transresistance Amplifier-a Current-to-Voltage Converter
544(2)
10.9.3 The Noninverting Amplifier
546(2)
10.9.4 The Unity-Gain Buffer, or Voltage Follower
548(3)
10.9.5 The Summing Amplifier
551(2)
10.9.6 The Difference Amplifier
553(2)
10.10 Frequency Dependent Feedback
555(19)
10.10.1 Bode Plots
556(1)
10.10.2 The Low-Pass Amplifier
556(3)
10.10.3 The High-Pass Amplifier
559(3)
10.10.4 Band-Pass Amplifiers
562(3)
10.10.5 An Active Low-Pass Filter
565(4)
10.10.6 An Active High-Pass Filter
569(1)
10.10.7 The Integrator
570(3)
10.10.8 The Differentiator
573(1)
Summary
574(1)
Key Terms
575(1)
References
576(1)
Additional Reading
576(1)
Problems
576(11)
Chapter 11 Nonideal Operational Amplifiers And Feedback Amplifier Stability
587(98)
11.1 Classic Feedback Systems
588(2)
11.1.1 Closed-Loop Gain Analysis
589(1)
11.1.2 Gain Error
589(1)
11.2 Analysis of Circuits Containing Nonideal Operational Amplifiers
590(12)
11.2.1 Finite Open-Loop Gain
590(3)
11.2.2 Nonzero Output Resistance
593(4)
11.2.3 Finite Input Resistance
597(4)
11.2.4 Summary of Nonideal Inverting and Noninverting Amplifiers
601(1)
11.3 Series and Shunt Feedback Circuits
602(1)
11.3.1 Feedback Amplifier Categories
602(1)
11.3.2 Voltage Amplifiers-Series-Shunt Feedback
603(1)
11.3.3 Transimpedance Amplifiers-Shunt-Shunt Feedback
603(1)
11.3.4 Current Amplifiers-Shunt-Series Feedback
603(1)
11.3.5 Transconductance Amplifiers-Series-Series Feedback
603(1)
11.4 Unified Approach to Feedback Amplifier Gain Calculation
603(1)
11.4.1 Closed-Loop Gain Analysis
604(1)
11.4.2 Resistance Calculations Using Blackman's Theorem
604(1)
11.5 Series-Shunt Feedback-Voltage Amplifiers
604(7)
11.5.1 Closed-Loop Gain Calculation
605(1)
11.5.2 Input Resistance Calculations
605(1)
11.5.3 Output Resistance Calculations
606(1)
11.5.4 Series-Shunt Feedback Amplifier Summary
607(4)
11.6 Shunt-Shunt Feedback-Transresistance Amplifiers
611(5)
11.6.1 Closed-Loop Gain Calculation
611(1)
11.6.2 Input Resistance Calculations
612(1)
11.6.3 Output Resistance Calculations
612(1)
11.6.4 Shunt-Shunt Feedback Amplifier Summary
613(3)
11.7 Series-Series Feedback-Transconductance Amplifiers
616(4)
11.7.1 Closed-Loop Gain Calculation
617(1)
11.7.2 Input Resistance Calculation
617(1)
11.7.3 Output Resistance Calculation
618(1)
11.7.4 Series-Series Feedback Amplifier Summary
618(2)
11.8 Shunt-Series Feedback-Current Amplifiers
620(5)
11.8.1 Closed-Loop Gain Calculation
621(1)
11.8.2 Input Resistance Calculation
621(1)
11.8.3 Output Resistance Calculation
622(1)
11.8.4 Series-Series Feedback Amplifier Summary
622(3)
11.9 Finding the Loop Gain Using Successive Voltage and Current Injection
625(3)
11.9.1 Simplifications
628(1)
11.10 Distortion Reduction through the Use of Feedback
628(1)
11.11 dc Error Sources and Output Range Limitations
629(8)
11.11.1 Input-Offset Voltage
629(2)
11.11.2 Offset-Voltage Adjustment
631(1)
11.11.3 Input-Bias and Offset Currents
632(2)
11.11.4 Output Voltage and Current Limits
634(3)
11.12 Common-Mode Rejection and Input Resistance
637(10)
11.12.1 Finite Common-Mode Rejection Ratio
637(1)
11.12.2 Why Is CMRR Important?
638(3)
11.12.3 Voltage-Follower Gain Error due to CMRR
641(3)
11.12.4 Common-Mode Input Resistance
644(1)
11.12.5 An Alternate Interpretation of CMRR
645(1)
11.12.6 Power Supply Rejection Ratio
645(2)
11.13 Frequency Response and Bandwidth of Operational Amplifiers
647(12)
11.13.1 Frequency Response of the Noninverting Amplifier
649(3)
11.13.2 Inverting Amplifier Frequency Response
652(2)
11.13.3 Using Feedback to Control Frequency Response
654(2)
11.13.4 Large-Signal Limitations-Slew Rate and Full-Power Bandwidth
656(1)
11.13.5 Macro Model for Operational Amplifier Frequency Response
657(1)
11.13.6 Complete Op Amp Macro Models in SPICE
658(1)
11.13.7 Examples of Commercial General-Purpose Operational Amplifiers
658(1)
11.14 Stability of Feedback Amplifiers
659(11)
11.14.1 The Nyquist Plot
659(1)
11.14.2 First-Order Systems
660(1)
11.14.3 Second-Order Systems and Phase Margin
661(1)
11.14.4 Step Response and Phase Margin
662(3)
11.14.5 Third-Order Systems and Gain Margin
665(1)
11.14.6 Determining Stability from the Bode Plot
666(4)
Summary
670(2)
Key Terms
672(1)
References
672(1)
Problems
673(12)
Chapter 12 Operational Amplifier Applications
685(85)
12.1 Cascaded Amplifiers
686(13)
12.1.1 Two-Port Representations
686(2)
12.1.2 Amplifier Terminology Review
688(3)
12.1.3 Frequency Response of Cascaded Amplifiers
691(8)
12.2 The Instrumentation Amplifier
699(3)
12.3 Active Filters
702(10)
12.3.1 Low-Pass Filter
702(4)
12.3.2 A High-Pass Filter with Gain
706(2)
12.3.3 Band-Pass Filter
708(2)
12.3.4 Sensitivity
710(1)
12.3.5 Magnitude and Frequency Scaling
711(1)
12.4 Switched-Capacitor Circuits
712(7)
12.4.1 A Switched-Capacitor Integrator
712(2)
12.4.2 Noninverting SC Integrator
714(2)
12.4.3 Switched-Capacitor Filters
716(3)
12.5 Digital-to-Analog Conversion
719(7)
12.5.1 D/A Converter Fundamentals
719(1)
12.5.2 D/A Converter Errors
720(2)
12.5.3 Digital-to-Analog Converter Circuits
722(4)
12.6 Analog-to-Digital Conversion
726(14)
12.6.1 A/D Converter Fundamentals
727(1)
12.6.2 Analog-to-Digital Converter Errors
728(1)
12.6.3 Basic A/D Conversion Techniques
729(11)
12.7 Oscillators
740(5)
12.7.1 The Barkhausen Criteria for Oscillation
740(1)
12.7.2 Oscillators Employing Frequency-Selective RC Networks
741(4)
12.8 Nonlinear Circuit Applications
745(3)
12.8.1 A Precision Half-Wave Rectifier
745(1)
12.8.2 Nonsaturating Precision-Rectifier Circuit
746(2)
12.9 Circuits Using Positive Feedback
748(7)
12.9.1 The Comparator and Schmitt Trigger
748(2)
12.9.2 The Astable Multivibrator
750(1)
12.9.3 The Monostable Multivibrator or One Shot
751(4)
Summary
755(2)
Key Terms
757(1)
Additional Reading
758(1)
Problems
758(12)
Chapter 13 Small-Signal Modeling And Linear Amplification
770(71)
13.1 The Transistor as an Amplifier
771(3)
13.1.1 The BJT Amplifier
772(1)
13.1.2 The MOSFET Amplifier
773(1)
13.2 Coupling and Bypass Capacitors
774(2)
13.3 Circuit Analysis Using dc and ac Equivalent Circuits
776(4)
13.3.1 Menu for dc and ac Analysis
776(4)
13.4 Introduction to Small-Signal Modeling
780(3)
13.4.1 Graphical Interpretation of the Small-Signal Behavior of the Diode
780(1)
13.4.2 Small-Signal Modeling of the Diode
781(2)
13.5 Small-Signal Models for Bipolar Junction Transistors
783(9)
13.5.1 The Hybrid-Pi Model
785(1)
13.5.2 Graphical Interpretation of the Transconductance
786(1)
13.5.3 Small-Signal Current Gain
786(1)
13.5.4 The Intrinsic Voltage Gain of the BJT
787(1)
13.5.5 Equivalent Forms of the Small-Signal Model
788(1)
13.5.6 Simplified Hybrid Pi Model
789(1)
13.5.7 Definition of a Small Signal for the Bipolar Transistor
789(2)
13.5.8 Small-Signal Model for the pnp Transistor
791(1)
13.5.9 ac Analysis versus Transient Analysis in SPICE
792(1)
13.6 The Common-Emitter (C-E) Amplifier
792(2)
13.6.1 Terminal Voltage Gain
792(2)
13.6.2 Input Resistance
794(1)
13.6.3 Signal Source Voltage Gain
794(1)
13.7 Important Limits and Model Simplifications
794(5)
13.7.1 A Design Guide for the Common-Emitter Amplifier
795(1)
13.7.2 Upper Bound on the Common-Emitter Gain
796(1)
13.7.3 Small-Signal Limit for the Common-Emitter Amplifier
796(3)
13.8 Small-Signal Models for Field-Effect Transistors
799(7)
13.8.1 Small-Signal Model for the MOSFET
799(2)
13.8.2 Intrinsic Voltage Gain of the MOSFET
801(1)
13.8.3 Definition of Small-Signal Operation for the MOSFET
802(1)
13.8.4 Body Effect in the Four-Terminal MOSFET
803(1)
13.8.5 Small-Signal Model for the PMOS Transistor
804(1)
13.8.6 Small-Signal Model for the Junction Field-Effect Transistor
805(1)
13.9 Summary and Comparison of the Small-Signal Models of the BJT and FET
806(3)
13.10 The Common-Source Amplifier
809(13)
13.10.1 Common-Source Terminal Voltage Gain
810(1)
13.10.2 Signal Source Voltage Gain for the Common-Source Amplifier
810(1)
13.10.3 A Design Guide for the Common-Source Amplifier
810(1)
13.10.4 Small-Signal Limit for the Common-Source Amplifier
811(2)
13.10.5 Input Resistances of the Common-Emitter and Common-Source Amplifiers
813(3)
13.10.6 Common-Emitter and Common-Source Output Resistances
816(6)
13.10.7 Comparison of the Three Amplifier Examples
822(1)
13.11 Common-Emitter and Common-Source Amplifier Summary
822(1)
13.11.1 Guidelines for Neglecting the Transistor Output Resistance
823(1)
13.12 Amplifier Power and Signal Range
823(4)
13.12.1 Power Dissipation
823(1)
13.12.2 Signal Range
824(3)
Summary
827(1)
Key Terms
828(1)
Problems
829(12)
Chapter 14 Single-Transistor Amplifiers
841(111)
14.1 Amplifier Classification
842(6)
14.1.1 Signal Injection and Extraction-the BJT
842(1)
14.1.2 Signal Injection and Extraction-the FET
843(1)
14.1.3 Common-Emitter (C-E) and Common-Source (C-S) Amplifiers
844(1)
14.1.4 Common-Collector (C-C) and Common-Drain (C-D) Topologies
845(2)
14.1.5 Common-Base (C-B) and Common-Gate (C-G) Amplifiers
847(1)
14.1.6 Small-Signal Model Review
848(1)
14.2 Inverting Amplifiers-Common-Emitter and Common-Source Circuits
848(22)
14.2.1 The Common-Emitter (C-E) Amplifier
848(13)
14.2.2 Common-Emitter Example Comparison
861(1)
14.2.3 The Common-Source Amplifier
861(3)
14.2.4 Small-Signal Limit for the Common-Source Amplifier
864(4)
14.2.5 Common-Emitter and Common-Source Amplifier Characteristics
868(1)
14.2.6 C-E/C-S Amplifier Summary
869(1)
14.2.7 Equivalent Transistor Representation of the Generalized C-E/C-S Transistor
869(1)
14.3 Follower Circuits-Common-Collector and Common-Drain Amplifiers
870(8)
14.3.1 Terminal Voltage Gain
870(1)
14.3.2 Input Resistance
871(1)
14.3.3 Signal Source Voltage Gain
872(1)
14.3.4 Follower Signal Range
872(1)
14.3.5 Follower Output Resistance
873(1)
14.3.6 Current Gain
874(1)
14.3.7 C-C/C-D Amplifier Summary
874(4)
14.4 Noninverting Amplifiers-Common-Base and Common-Gate Circuits
878(9)
14.4.1 Terminal Voltage Gain and Input Resistance
879(1)
14.4.2 Signal Source Voltage Gain
880(1)
14.4.3 Input Signal Range
881(1)
14.4.4 Resistance at the Collector and Drain Terminals
881(1)
14.4.5 Current Gain
882(1)
14.4.6 Overall Input and Output Resistances for the Noninverting Amplifiers
883(3)
14.4.7 C-B/C-G Amplifier Summary
886(1)
14.5 Amplifier Prototype Review and Comparison
887(4)
14.5.1 The BJT Amplifiers
887(2)
14.5.2 The FET Amplifiers
889(2)
14.6 Common-Source Amplifiers Using MOS Inverters
891(7)
14.6.1 Voltage Gain Estimate
892(1)
14.6.2 Detailed Analysis
893(1)
14.6.3 Alternative Loads
894(1)
14.6.4 Input and Output Resistances
895(3)
14.7 Coupling and Bypass Capacitor Design
898(11)
14.7.1 Common-Emitter and Common-Source Amplifiers
898(5)
14.7.2 Common-Collector and Common-Drain Amplifiers
903(2)
14.7.3 Common-Base and Common-Gate Amplifiers
905(3)
14.7.4 Setting Lower Cutoff Frequency fL
908(1)
14.8 Amplifier Design Examples
909(14)
14.8.1 Monte Carlo Evaluation of the Common-Base Amplifier Design
918(5)
14.9 Multistage ac-Coupled Amplifiers
923(11)
14.9.1 A Three-Stage ac-Coupled Amplifier
923(2)
14.9.2 Voltage Gain
925(2)
14.9.3 Input Resistance
927(1)
14.9.4 Signal Source Voltage Gain
927(1)
14.9.5 Output Resistance
927(1)
14.9.6 Current and Power Gain
928(1)
14.9.7 Input Signal Range
929(3)
14.9.8 Estimating the Lower Cutoff Frequency of the Multistage Amplifier
932(2)
Summary
934(1)
Key Terms
935(1)
Additional Reading
936(1)
Problems
936(16)
Chapter 15 Differential Amplifiers And Operational Amplifier Design
952(79)
15.1 Differential Amplifiers
953(23)
15.1.1 Bipolar and MOS Differential Amplifiers
953(1)
15.1.2 dc Analysis of the Bipolar Differential Amplifier
954(2)
15.1.3 Transfer Characteristic for the Bipolar Differential Amplifier
956(1)
15.1.4 ac Analysis of the Bipolar Differential Amplifier
957(1)
15.1.5 Differential-Mode Gain and Input and Output Resistances
958(2)
15.1.6 Common-Mode Gain and Input Resistance
960(2)
15.1.7 Common-Mode Rejection Ratio (CMRR)
962(1)
15.1.8 Analysis Using Differential- and Common-Mode Half-Circuits
963(3)
15.1.9 Biasing with Electronic Current Sources
966(1)
15.1.10 Modeling the Electronic Current Source in SPICE
967(1)
15.1.11 dc Analysis of the MOSFET Differential Amplifier
967(3)
15.1.12 Differential-Mode Input Signals
970(1)
15.1.13 Small-Signal Transfer Characteristic for the MOS Differential Amplifier
971(1)
15.1.14 Common-Mode Input Signals
971(1)
15.1.15 Model for Differential Pairs
972(4)
15.2 Evolution to Basic Operational Amplifiers
976(16)
15.2.1 A Two-Stage Prototype for an Operational Amplifier
977(5)
15.2.2 Improving the Op Amp Voltage Gain
982(1)
15.2.3 Darlington Pairs
983(1)
15.2.4 Output Resistance Reduction
984(4)
15.2.5 A CMOS Operational Amplifier Prototype
988(2)
15.2.6 BiCMOS Amplifiers
990(1)
15.2.7 All Transistor Implementations
990(2)
15.3 Output Stages
992(10)
15.3.1 The Source Follower-a Class-A Output Stage
992(1)
15.3.2 Efficiency of Class-A Amplifiers
993(1)
15.3.3 Class-B Push-Pull Output Stage
994(2)
15.3.4 Class-AB Amplifiers
996(1)
15.3.5 Class-AB Output Stages for Operational Amplifiers
997(1)
15.3.6 Short-Circuit Protection
997(2)
15.3.7 Transformer Coupling
999(3)
15.4 Electronic Current Sources
1002(11)
15.4.1 Single-Transistor Current Sources
1003(1)
15.4.2 Figure of Merit for Current Sources
1003(1)
15.4.3 Higher Output Resistance Sources
1004(1)
15.4.4 Current Source Design Examples
1005(8)
Summary
1013(1)
Key Terms
1014(1)
References
1015(1)
Additional Reading
1015(1)
Problems
1015(16)
Chapter 16 Analog Integrated Circuit Design Techniques
1031(82)
16.1 Circuit Element Matching
1032(1)
16.2 Current Mirrors
1033(15)
16.2.1 dc Analysis of the MOS Transistor Current Mirror
1034(2)
16.2.2 Changing the MOS Mirror Ratio
1036(1)
16.2.3 dc Analysis of the Bipolar Transistor Current Mirror
1037(2)
16.2.4 Altering the BJT Current Mirror Ratio
1039(1)
16.2.5 Multiple Current Sources
1040(1)
16.2.6 Buffered Current Mirror
1041(1)
16.2.7 Output Resistance of the Current Mirrors
1042(1)
16.2.8 Two-Port Model for the Current Mirror
1043(2)
16.2.9 The Widlar Current Source
1045(3)
16.2.10 The MOS Version of the Widlar Source
1048(1)
16.3 High-Output-Resistance Current Mirrors
1048(9)
16.3.1 The Wilson Current Sources
10491
16.3.2 Output Resistance of the Wilson Source
1050(1)
16.3.3 Cascode Current Sources
1051(1)
16.3.4 Output Resistance of the Cascode Sources
1052(1)
16.3.5 Regulated Cascode Current Source
1053(1)
16.3.6 Current Mirror Summary
1054(3)
16.4 Reference Current Generation
1057(1)
16.5 Supply-Independent Biasing
1058(4)
16.5.1 A VBE-Based Reference
1058(1)
16.5.2 The Widlar Source
1058(1)
16.5.3 Power-Supply-Independent Bias Cell
1059(1)
16.5.4 A Supply-Independent MOS Reference Cell
1060(2)
16.6 The Bandgap Reference
1062(4)
16.7 The Current Mirror as an Active Load
1066(11)
16.7.1 CMOS Differential Amplifier with Active Load
1066(7)
16.7.2 Bipolar Differential Amplifier with Active Load
1073(4)
16.8 Active Loads in Operational Amplifiers
1077(5)
16.8.1 CMOS Op Amp Voltage Gain
1077(1)
16.8.2 dc Design Considerations
1078(2)
16.8.3 Bipolar Operational Amplifiers
1080(1)
16.8.4 Input Stage Breakdown
1081(1)
16.9 The µA741 Operational Amplifier
1082(13)
16.9.1 Overall Circuit Operation
1082(1)
16.9.2 Bias Circuitry
1083(1)
16.9.3 dc Analysis of the 741 Input Stage
1084(3)
16.9.4 ac Analysis of the 741 Input Stage
1087(1)
16.9.5 Voltage Gain of the Complete Amplifier
1088(4)
16.9.6 The 741 Output Stage
1092(2)
16.9.7 Output Resistance
1094(1)
16.9.8 Short-Circuit Protection
1094(1)
16.9.9 Summary of the µA741 Operational Amplifier Characteristics
1094(1)
16.10 The Gilbert Analog Multiplier
1095(2)
Summary
1097(1)
Key Terms
1098(1)
References
1099(1)
Problems
1099(14)
Chapter 17 Amplifier Frequency Response
1113(104)
17.1 Amplifier Frequency Response
1114(5)
17.1.1 Low-Frequency Response
1115(1)
17.1.2 Estimating (ωL in the Absence of a Dominant Pole
1115(3)
17.1.3 High-Frequency Response
1118(1)
17.1.4 Estimating wH in the Absence of a Dominant Pole
1118(1)
17.2 Direct Determination of the Low-Frequency Poles and Zeros-the Common-Source Amplifier
1119(5)
17.3 Estimation of (ωL Using the Short-Circuit Time-Constant Method
1124(9)
17.3.1 Estimate of ωL for the Common-Emitter Amplifier
1125(4)
17.3.2 Estimate of ωL for the Common-Source Amplifier
1129(1)
17.3.3 Estimate of ωL for the Common-Base Amplifier
1130(1)
17.3.4 Estimate of ωL for the Common-Gate Amplifier
1131(1)
17.3.5 Estimate of ωL for the Common-Collector Amplifier
1132(1)
17.3.6 Estimate of ωL for the Common-Drain Amplifier
1132(1)
17.4 Transistor Models at High Frequencies
1133(7)
17.4.1 Frequency-Dependent Hybrid-Pi Model for the Bipolar Transistor
1133(1)
17.4.2 Modeling Cπ and Cµ in SPICE
1134(1)
17.4.3 Unity-Gain Frequency fT
1134(3)
17.4.4 High-Frequency Model for the FET
1137(1)
17.4.5 Modeling CGS and CGD in SPICE
1138(1)
17.4.6 Channel Length Dependence of fT
1138(2)
17.4.7 Limitations of the High-Frequency Models
1140(1)
17.5 Base and Gate Resistances in the Small-Signal Models
1140(2)
17.5.1 Effect of Base and Gate Resistances on Midband Amplifiers
1141(1)
17.6 High-Frequency Common-Emitter and Common-Source Amplifier Analysis
1142(18)
17.6.1 The Miller Effect
1144(2)
17.6.2 Common-Emitter and Common-Source Amplifier High-Frequency Response
1146(2)
17.6.3 Direct Analysis of the Common-Emitter Transfer Characteristic
1148(1)
17.6.4 Poles of the Common-Emitter Amplifier
1149(3)
17.6.5 Dominant Pole for the Common-Source Amplifier
1152(2)
17.6.6 Estimation of ωH Using the Open-Circuit Time-Constant Method
1154(1)
17.6.7 Common-Source Amplifier with Source Degeneration Resistance
1155(2)
17.6.8 Poles of the Common-Emitter with Emitter Degeneration Resistance
1157(3)
17.7 Common-Base and Common-Gate Amplifier High-Frequency Response
1160(2)
17.8 Common-Collector and Common-Drain Amplifier High-Frequency Response
1162(4)
17.8.1 Frequency Response of the Complementary Emitter Follower
1165(1)
17.9 Single-Stage Amplifier High-Frequency Response Summary
1166(2)
17.9.1 Amplifier Gain-Bandwidth Limitations
1167(1)
17.10 Frequency Response of Multistage Amplifiers
1168(13)
17.10.1 Differential Amplifier
1168(2)
17.10.2 The Common-Collector/Common-Base Cascade
1170(1)
17.10.3 High-Frequency Response of the Cascode Amplifier
1171(1)
17.10.4 Cutoff Frequency for the Current Mirror
1172(1)
17.10.5 Three-Stage Amplifier Example
1173(8)
17.11 Introduction to Radio Frequency Circuits
1181(12)
17.11.1 Radio Frequency Amplifiers
1182(1)
17.11.2 The Shunt-Peaked Amplifier
1182(2)
17.11.3 Single-Tuned Amplifier
1184(2)
17.11.4 Use of a Tapped Inductor-the Auto Transformer
1186(2)
17.11.5 Multiple Tuned Circuits-Synchronous and Stagger Tuning
1188(1)
17.11.6 Common-Source Amplifier with Inductive Degeneration
1189(4)
17.12 Mixers and Balanced Modulators
1193(10)
17.12.1 Introduction to Mixer Operation
1193(1)
17.12.2 A Single-Balanced Mixer
1194(1)
17.12.3 The Differential Pair as a Single-Balanced Mixer
1195(2)
17.12.4 A Double-Balanced Mixer
1197(2)
17.12.5 The Jones Mixer-a Double-Balanced Mixer/Modulator
1199(4)
Summary
1203(1)
Key Terms
1204(1)
References
1204(1)
Problems
1205(12)
Chapter 18 Transistor Feedback Amplifiers And Oscillators
1217(74)
18.1 Basic Feedback System Review
1218(3)
18.1.1 Closed-Loop Gain
1218(1)
18.1.2 Closed-Loop Impedances
1219(1)
18.1.3 Feedback Effects
1219(2)
18.2 Feedback Amplifier Analysis at Midband
1221(3)
18.2.1 Closed-Loop Gain
1221(1)
18.2.2 Input Resistance
1222(1)
18.2.3 Output Resistance
1222(1)
18.2.4 Offset Voltage Calculation
1223(1)
18.3 Feedback Amplifier Circuit Examples
1224(20)
18.3.1 Series-Shunt Feedback-Voltage Amplifiers
1224(5)
18.3.2 Differential Input Series-Shunt Voltage Amplifier
1229(3)
18.3.3 Shunt-Shunt Feedback-Transresistance Amplifiers
1232(6)
18.3.4 Series-Series Feedback-Transconductance Amplifiers
1238(3)
18.3.5 Shunt-Series Feedback-Current Amplifiers
1241(3)
18.4 Review of Feedback Amplifier Stability
1244(9)
18.4.1 Closed-Loop Response of the Uncompensated Amplifier
1245(1)
18.4.2 Phase Margin
1246(4)
18.4.3 Higher Order Effects
1250(1)
18.4.4 Response of the Compensated Amplifier
1251(2)
18.4.5 Small-Signal Limitations
1253(1)
18.5 Single-Pole Operational Amplifier Compensation
1253(15)
18.5.1 Three-Stage Op-Amp Analysis
1254(2)
18.5.2 Transmission Zeros in FET Op Amps
1256(1)
18.5.3 Bipolar Amplifier Compensation
1257(1)
18.5.4 Slew Rate of the Operational Amplifier
1258(1)
18.5.5 Relationships between Slew Rate and Gain-Bandwidth Product
1259(9)
18.6 High-Frequency Oscillators
1268(10)
18.6.1 The Colpitts Oscillator
1269(1)
18.6.2 The Hartley Oscillator
1270(1)
18.6.3 Amplitude Stabilization in LC Oscillators
1271(1)
18.6.4 Negative Resistance in Oscillators
1271(1)
18.6.5 Negative Gm Oscillator
1272(2)
18.6.6 Crystal Oscillators
1274(4)
Summary
1278(2)
Key Terms
1280(1)
References
1280(1)
Problems
1280
Appendices
A Standard Discrete Component Values
1291(3)
B Solid-State Device Models and SPICE Simulation Parameters
1294(5)
C Two-Port Review
1299(4)
Index 1303
Richard Jaeger earned his bachelor's, master's, and doctoral degrees in electrical engineering from the University of Florida. Professor Jaeger was one of the first three faculty members appointed Distinguished University Professor by Auburn University. His teaching awards include the Birdsong Merit Teaching Award and selection by ECE undergraduate students as Outstanding Electrical Engineering Faculty Member. In 1995 he was named Distinguished Graduate Faculty Lecturer. His current research interests include solid-state circuits and devices, electronic packaging, piezoresistive stress sensors, high heat flux cooling, low temperature electronics, VLSI design, and noise in electronic devices and circuits.





Travis Blalock is an Associate Professor in the Department of Electrical and Computer Engineering at University of Virginia.