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Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault 2010 ed. [Kõva köide]

  • Formaat: Hardback, 257 pages, kõrgus x laius: 235x155 mm, kaal: 1230 g, XIV, 257 p., 1 Hardback
  • Sari: Frontiers in Electronic Testing 43
  • Ilmumisaeg: 07-Dec-2009
  • Kirjastus: Springer
  • ISBN-10: 9048132819
  • ISBN-13: 9789048132812
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  • Formaat: Hardback, 257 pages, kõrgus x laius: 235x155 mm, kaal: 1230 g, XIV, 257 p., 1 Hardback
  • Sari: Frontiers in Electronic Testing 43
  • Ilmumisaeg: 07-Dec-2009
  • Kirjastus: Springer
  • ISBN-10: 9048132819
  • ISBN-13: 9789048132812
Teised raamatud teemal:
"Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance. Models in Hardware Testing treats models and especially fault models in hardware testing in a comprehensive way not found anywhere else. Engineers who are responsible for product quality and test coverage, students who want to learn about quality assessment for new technologies or lecturers who are interested in the most recent advances in model based hardware testing will take benefits from reading. The material collected in Models in Hardware Testing was prepared for the forum in honor of Christian Landrault in connection with the European Test Symposium 2009."--Publisher's website.

Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.



Model based testing is the most powerful technique for testing hardware and software systems. This book describes the use of models at all the levels of hardware testing. It includes a description of fault models for nanoscaled CMOS technology.

Contributing Authors. Preface. To Christian: a Real Test & Taste Expert. From LAAS to LIRMM and Beyond. 1: Open Defects in Nanometer Technologies; J. Figueras, et al. 2: Models for Bridging Defects; M. Renovell, et al. 3: Models for Delay Faults; S. M. Reddy. 4: Fault Modeling for Simulation and ATPG; B. Becker, I. Polian. 5: Generalized Fault Modeling for Logic Diagnosis; H.-J. Wunderlich, S. Holst. 6: Models in Memory Testing, From functional testing to defect-based testing; S. Di Carlo, P. Prinetto. 7: Models for Power-Aware Testing; P. Girard, H.-J. Wunderlich. 8: Physical Fault Models and Fault Tolerance; J. Arlat, Y. Crouzet. Index.