Preface |
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xi | |
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1 | (26) |
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Why build integrated circuits? |
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1 | (3) |
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Integrated circuit manufacturing |
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4 | (5) |
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4 | (2) |
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6 | (3) |
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9 | (1) |
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10 | (2) |
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Integrated circuit design techniques |
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12 | (10) |
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13 | (2) |
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15 | (5) |
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20 | (2) |
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22 | (3) |
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25 | (1) |
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25 | (1) |
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25 | (2) |
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27 | (56) |
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27 | (1) |
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28 | (14) |
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29 | (5) |
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34 | (1) |
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35 | (4) |
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Process parameters and variations |
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39 | (3) |
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42 | (7) |
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42 | (4) |
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46 | (3) |
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49 | (10) |
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49 | (3) |
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52 | (2) |
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54 | (3) |
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57 | (2) |
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59 | (18) |
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59 | (4) |
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63 | (2) |
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Hierarchical stick diagrams |
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65 | (5) |
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Layout design and analysis tools |
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70 | (4) |
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74 | (3) |
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77 | (1) |
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78 | (5) |
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83 | (66) |
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83 | (1) |
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Combinational logic functions |
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83 | (3) |
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Static complementary gates |
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86 | (35) |
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86 | (5) |
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91 | (4) |
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95 | (4) |
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99 | (3) |
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102 | (6) |
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108 | (4) |
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112 | (3) |
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115 | (1) |
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Advanced wire delay models |
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116 | (3) |
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Advanced transistor characteristics |
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119 | (2) |
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121 | (5) |
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122 | (2) |
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124 | (2) |
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Combinational logic networks |
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126 | (12) |
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126 | (5) |
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Combinational network delay |
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131 | (7) |
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Automated logic optimization |
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138 | (1) |
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Combinational logic testing |
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138 | (5) |
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138 | (3) |
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Combinational network testing |
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141 | (2) |
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143 | (1) |
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144 | (5) |
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149 | (58) |
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149 | (1) |
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149 | (9) |
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Categories of memory elements |
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149 | (2) |
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151 | (6) |
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157 | (1) |
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Sequential systems and clocking disciplines |
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158 | (18) |
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One-phase systems for flip-flops |
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161 | (1) |
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Two-phase systems for latches |
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161 | (9) |
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170 | (1) |
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171 | (1) |
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Advanced performance analysis |
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172 | (4) |
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176 | (17) |
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Structural specification of sequential machines |
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176 | (2) |
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State transition graphs and tables |
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178 | (9) |
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187 | (6) |
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193 | (2) |
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195 | (8) |
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203 | (1) |
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203 | (4) |
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207 | (50) |
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207 | (1) |
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208 | (13) |
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209 | (9) |
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Standard cell layout design |
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218 | (3) |
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221 | (2) |
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223 | (5) |
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228 | (3) |
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231 | (8) |
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239 | (7) |
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241 | (1) |
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241 | (4) |
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The three-transistor DRAM |
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245 | (1) |
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246 | (3) |
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Programmable logic arrays |
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249 | (4) |
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253 | (1) |
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253 | (4) |
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257 | (36) |
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257 | (1) |
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257 | (20) |
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Block placement and channel definition |
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261 | (5) |
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266 | (2) |
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268 | (1) |
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269 | (2) |
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271 | (4) |
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275 | (1) |
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276 | (1) |
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277 | (9) |
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277 | (4) |
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281 | (1) |
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282 | (4) |
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286 | (1) |
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287 | (6) |
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293 | (44) |
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293 | (1) |
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294 | (13) |
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Register-transfer simulation programs |
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295 | (2) |
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Data path-controller architectures |
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297 | (1) |
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298 | (9) |
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307 | (21) |
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Functional modeling programs |
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308 | (1) |
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309 | (11) |
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320 | (6) |
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326 | (2) |
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328 | (4) |
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332 | (1) |
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333 | (4) |
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337 | (36) |
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337 | (1) |
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338 | (18) |
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Timer specification and architecture |
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338 | (2) |
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340 | (7) |
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347 | (6) |
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353 | (3) |
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356 | (13) |
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356 | (5) |
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361 | (3) |
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364 | (1) |
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365 | (4) |
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369 | (1) |
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370 | (3) |
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Analysis and Synthesis Algorithms |
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373 | (44) |
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373 | (1) |
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374 | (1) |
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375 | (4) |
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375 | (2) |
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377 | (2) |
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379 | (8) |
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380 | (3) |
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383 | (2) |
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385 | (2) |
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387 | (2) |
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Timing analysis and optimization |
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389 | (5) |
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394 | (11) |
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Technology independent logic optimization |
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395 | (8) |
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Technology-dependent logic optimizations |
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403 | (2) |
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405 | (3) |
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Sequential machine optimizations |
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408 | (1) |
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409 | (2) |
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411 | (1) |
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412 | (5) |
Appendix A A Chip Designer's Lexicon |
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417 | (4) |
Appendix B Chip Design Projects |
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421 | (8) |
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421 | (2) |
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B.2 Project proposal and specification |
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423 | (1) |
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424 | (3) |
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B.4 Design checkpoints and documentation |
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427 | (2) |
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427 | (1) |
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427 | (1) |
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427 | (2) |
Appendix C Design Modeling |
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429 | (18) |
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429 | (1) |
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C.2 Hardware modeling in VHDL |
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429 | (6) |
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C.3 Hardware modeling in C |
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435 | (12) |
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438 | (5) |
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443 | (4) |
References |
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447 | (12) |
Index |
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459 | |