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Modern VLSI Design: A Systems Approach [Kõva köide]

  • Formaat: Hardback, 496 pages, kõrgus x laius x paksus: 242x182x21 mm, kaal: 900 g
  • Ilmumisaeg: 01-Feb-1994
  • Kirjastus: Prentice Hall
  • ISBN-10: 0135883776
  • ISBN-13: 9780135883778
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  • Formaat: Hardback, 496 pages, kõrgus x laius x paksus: 242x182x21 mm, kaal: 900 g
  • Ilmumisaeg: 01-Feb-1994
  • Kirjastus: Prentice Hall
  • ISBN-10: 0135883776
  • ISBN-13: 9780135883778
Teised raamatud teemal:
This comprehensive, detailed view of up-to-date VLSI design techniques for custom digital integrated circuit design shows readers how to design a variety of digital chips -- ranging from CPUs to interface logic -- starting only with bare silicon. It covers all phases of the IC design process, and provides insight into how modern computer-aided (CAD) methods should be used in the process. Readers will understand the complete IC design process -- from defining what the chip does to designing a chips layout and preparing the chip for manufacturing test. KEY TOPICS: Covers every phase of design -- from layout to architecture. Discusses design problems and techniques specific to custom IC design, and CMOS ICs in particular; and presents other techniques that are useful in almost any implementation technology -- gate arrays, programmable logic devices. etc. For computer scientists, electrical engineer, IC designers, and CAD engineers.
Preface xi
Digital Systems and VLSI
1(26)
Why build integrated circuits?
1(3)
Integrated circuit manufacturing
4(5)
Technology
4(2)
Economics
6(3)
CMOS technology
9(1)
Design and testability
10(2)
Integrated circuit design techniques
12(10)
Hierarchical design
13(2)
Design abstraction
15(5)
Computer-aided design
20(2)
A look ahead
22(3)
Summary
25(1)
References
25(1)
Problems
25(2)
Fabrication and Layout
27(56)
Introduction
27(1)
Components
28(14)
Transistors
29(5)
Wires and vias
34(1)
Parasitic elements
35(4)
Process parameters and variations
39(3)
Fabrication processes
42(7)
Fabrication steps
42(4)
Tub ties and latchup
46(3)
Design rules
49(10)
Fabrication errors
49(3)
Scalable design rules
52(2)
SCMOS design rules
54(3)
Technology trends
57(2)
Layout design and tools
59(18)
Layouts for circuits
59(4)
Stick diagrams
63(2)
Hierarchical stick diagrams
65(5)
Layout design and analysis tools
70(4)
Automatic layout
74(3)
References
77(1)
Problems
78(5)
Combinational Logic
83(66)
Introduction
83(1)
Combinational logic functions
83(3)
Static complementary gates
86(35)
Gate structures
86(5)
Basic gate layouts
91(4)
Simulation
95(4)
Logic levels
99(3)
Delay
102(6)
Power consumption
108(4)
Layout and parasitics
112(3)
Driving large loads
115(1)
Advanced wire delay models
116(3)
Advanced transistor characteristics
119(2)
Advanced gate circuits
121(5)
Pseudo-nMOS logic
122(2)
Domino logic
124(2)
Combinational logic networks
126(12)
Switch logic
126(5)
Combinational network delay
131(7)
Automated logic optimization
138(1)
Combinational logic testing
138(5)
Gate testing
138(3)
Combinational network testing
141(2)
References
143(1)
Problems
144(5)
Sequential Machines
149(58)
Introduction
149(1)
Latches and flip-flops
149(9)
Categories of memory elements
149(2)
Latches
151(6)
Flip-flops
157(1)
Sequential systems and clocking disciplines
158(18)
One-phase systems for flip-flops
161(1)
Two-phase systems for latches
161(9)
Clock period
170(1)
Clock generation
171(1)
Advanced performance analysis
172(4)
Sequential system design
176(17)
Structural specification of sequential machines
176(2)
State transition graphs and tables
178(9)
State assignment
187(6)
Design validation
193(2)
Sequential testing
195(8)
References
203(1)
Problems
203(4)
Subsystems
207(50)
Introduction
207(1)
Layout design methods
208(13)
Single-row layout design
209(9)
Standard cell layout design
218(3)
Combinational shifters
221(2)
Adders
223(5)
ALUs
228(3)
Multipliers
231(8)
High-density memory
239(7)
ROM
241(1)
Static RAM
241(4)
The three-transistor DRAM
245(1)
Data path design
246(3)
Programmable logic arrays
249(4)
References
253(1)
Problems
253(4)
Floorplanning
257(36)
Introduction
257(1)
Floorplanning methods
257(20)
Block placement and channel definition
261(5)
Global routing
266(2)
Switchbox routing
268(1)
Power distribution
269(2)
Clock distribution
271(4)
Floorplanning tips
275(1)
Design validation
276(1)
Off-chip connections
277(9)
Packages
277(4)
The I/O architecture
281(1)
Pad design
282(4)
References
286(1)
Problems
287(6)
Architecture Design
293(44)
Introduction
293(1)
Register-transfer design
294(13)
Register-transfer simulation programs
295(2)
Data path-controller architectures
297(1)
ASM chart design
298(9)
High-level synthesis
307(21)
Functional modeling programs
308(1)
Data
309(11)
Control
320(6)
Data and control
326(2)
Architecture testing
328(4)
References
332(1)
Problems
333(4)
Chip Design
337(36)
Introduction
337(1)
Kitchen timer chip
338(18)
Timer specification and architecture
338(2)
Architecture design
340(7)
Logic and layout design
347(6)
Design validation
353(3)
PDP-8 data path
356(13)
PDP-8 instruction set
356(5)
Register-transfer design
361(3)
Clocking and bus design
364(1)
Logic and layout design
365(4)
References
369(1)
Problems
370(3)
Analysis and Synthesis Algorithms
373(44)
Introduction
373(1)
CAD systems
374(1)
Simulation
375(4)
Event-driven simulation
375(2)
Switch simulation
377(2)
Layout synthesis
379(8)
Placement
380(3)
Global routing
383(2)
Detailed routing
385(2)
Layout analysis
387(2)
Timing analysis and optimization
389(5)
Logic synthesis
394(11)
Technology independent logic optimization
395(8)
Technology-dependent logic optimizations
403(2)
Test generation
405(3)
Sequential machine optimizations
408(1)
Scheduling and binding
409(2)
References
411(1)
Problems
412(5)
Appendix A A Chip Designer's Lexicon 417(4)
Appendix B Chip Design Projects 421(8)
B.1 Class project ideas
421(2)
B.2 Project proposal and specification
423(1)
B.3 Design plan
424(3)
B.4 Design checkpoints and documentation
427(2)
B.4.1 Subsystems check
427(1)
B.4.2 First layout check
427(1)
B.4.3 Project completion
427(2)
Appendix C Design Modeling 429(18)
C.1 Introduction
429(1)
C.2 Hardware modeling in VHDL
429(6)
C.3 Hardware modeling in C
435(12)
C.3.1 Simulator
438(5)
C.3.2 Sample execution
443(4)
References 447(12)
Index 459