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Multi-Core Embedded Systems [Pehme köide]

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  • Formaat: Paperback / softback, 502 pages, kõrgus x laius: 234x156 mm, kaal: 453 g
  • Ilmumisaeg: 19-Sep-2019
  • Kirjastus: CRC Press
  • ISBN-10: 0367384302
  • ISBN-13: 9780367384302
Teised raamatud teemal:
Multi-Core Embedded SystemsSuurem pilt
  • Formaat: Paperback / softback, 502 pages, kõrgus x laius: 234x156 mm, kaal: 453 g
  • Ilmumisaeg: 19-Sep-2019
  • Kirjastus: CRC Press
  • ISBN-10: 0367384302
  • ISBN-13: 9780367384302
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780367384302.html
Märksõnad:

Details a real-world product that applies a cutting-edge multi-core architecture



Increasingly demanding modern applications—such as those used in telecommunications networking and real-time processing of audio, video, and multimedia streams—require multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner.





Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. It offers an analysis that industry engineers and professionals will need to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth.





Discusses the available programming models spread across different abstraction levels





The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains—such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems, such as:









  • Architectures and interconnects








  • Embedded design methodologies








  • Mapping of applications








With numerous case studies, this volume presents an introduction to the fundamental aspects of developing modem embedded systems with many cores. The book also covers hardware and software resource management, multithreading, and multi-core programming challenges.

List of Figures xiii
List of Tables xxi
Foreword xxiii
Preface xxv
1 Multi-Core Architectures for Embedded Systems 1(30)
C.P. Ravikumar
1.1 Introduction
2(7)
1.1.1 What Makes Multiprocessor Solutions Attractive?
3(6)
1.2 Architectural Considerations
9(2)
1.3 Interconnection Networks
11(2)
1.4 Software Optimizations
13(1)
1.5 Case Studies
14(11)
1.5.1 HiBRID-SoC for Multimedia Signal Processing
14(2)
1.5.2 VIPER Multiprocessor SoC
16(1)
1.5.3 Defect-Tolerant and Reconfigurable MPSoC
17(1)
1.5.4 Homogeneous Multiprocessor for Embedded Printer Application
18(2)
1.5.5 General Purpose Multiprocessor DSP
20(1)
1.5.6 Multiprocessor DSP for Mobile Applications
21(2)
1.5.7 Multi-Core DSP Platforms
23(2)
1.6 Conclusions
25(1)
Review Questions
25(2)
Bibliography
27(4)
2 Application-Specific Customizable Embedded Systems 31(40)
Georgios Kornaros
2.1 Introduction
32(2)
2.2 Challenges and Opportunities
34(3)
2.2.1 Objectives
35(2)
2.3 Categorization
37(4)
2.3.1 Customized Application-Specific Processor Techniques
37(3)
2.3.2 Customized Application-Specific On-Chip Interconnect Techniques
40(1)
2.4 Configurable Processors and Instruction Set Synthesis
41(11)
2.4.1 Design Methodology for Processor Customization
43(1)
2.4.2 Instruction Set Extension Techniques
44(4)
2.4.3 Application-Specific Memory-Aware Customization
48(1)
2.4.4 Customizing On-Chip Communication Interconnect
48(1)
2.4.5 Customization of MPSoCs
49(3)
2.5 Reconfigurable Instruction Set Processors
52(2)
2.5.1 Warp Processing
53(1)
2.6 Hardware/Software Codesign
54(1)
2.7 Hardware Architecture Description Languages
55(3)
2.7.1 LISATek Design Platform
57(1)
2.8 Myths and Realities
58(2)
2.9 Case Study: Realizing Customizable Multi-Core Designs
60(2)
2.10 The Future: System Design with Customizable Architectures, Software, and Tools
62(1)
Review Questions
63(1)
Bibliography
63(8)
3 Power Optimization in Multi-Core System-on-Chip 71(40)
Massimo Conti
Simone Orcioni
Giovanni Vece
Stefano Gigli
3.1 Introduction
72(2)
3.2 Low Power Design
74(8)
3.2.1 Power Models
75(5)
3.2.2 Power Analysis Tools
80(2)
3.3 PKtool
82(5)
3.3.1 Basic Features
82(1)
3.3.2 Power Models
83(1)
3.3.3 Augmented Signals
84(1)
3.3.4 Power States
85(1)
3.3.5 Application Examples
86(1)
3.4 On-Chip Communication Architectures
87(3)
3.5 NOCEXplore
90(5)
3.5.1 Analysis
91(4)
3.6 DPM and DVS in Multi-Core Systems
95(5)
3.7 Conclusions
100(1)
Review Questions
101(1)
Bibliography
102(9)
4 Routing Algorithms for Irregular Mesh-Based Network-on- Chip 111(44)
Shu-Yen Lin
An-Yeu Wu
4.1 Introduction
112(1)
4.2 An Overview of Irregular Mesh Topology
113(2)
4.2.1 2D Mesh Topology
113(1)
4.2.2 Irregular Mesh Topology
113(2)
4.3 Fault-Tolerant Routing Algorithms for 2D Meshes
115(11)
4.3.1 Fault-Tolerant Routing Using Virtual Channels
116(1)
4.3.2 Fault-Tolerant Routing with Turn Model
117(9)
4.4 Routing Algorithms for Irregular Mesh Topology
126(10)
4.4.1 Traffic-Balanced OAPR Routing Algorithm
127(5)
4.4.2 Application-Specific Routing Algorithm
132(4)
4.5 Placement for Irregular Mesh Topology
136(7)
4.5.1 OIP Placements Based on Chen and Chiu's Algorithm
137(3)
4.5.2 OIP Placements Based on OAPR
140(3)
4.6 Hardware Efficient Routing Algorithms
143(8)
4.6.1 Turns-Table Routing (TT)
146(1)
4.6.2 XY-Deviation Table Routing (XYDT)
147(1)
4.6.3 Source Routing for Deviation Points (SRDP)
147(1)
4.6.4 Degree Priority Routing Algorithm
148(3)
4.7 Conclusions
151(1)
Review Questions
151(1)
Bibliography
151(4)
5 Debugging Multi-Core Systems-on-Chip 155(46)
Bart Vermeulen
Kees Goossens
5.1 Introduction
156(2)
5.2 Why Debugging Is Difficult
158(5)
5.2.1 Limited Internal Observability
158(1)
5.2.2 Asynchronicity and Consistent Global States
159(2)
5.2.3 Non-Determinism and Multiple Traces
161(2)
5.3 Debugging an SoC
163(6)
5.3.1 Errors
164(1)
5.3.2 Example Erroneous System
165(1)
5.3.3 Debug Process
166(3)
5.4 Debug Methods
169(5)
5.4.1 Properties
169(2)
5.4.2 Comparing Existing Debug Methods
171(3)
5.5 CSAR Debug Approach
174(4)
5.5.1 Communication-Centric Debug
175(1)
5.5.2 Scan-Based Debug
175(1)
5.5.3 Run/Stop-Based Debug
176(1)
5.5.4 Abstraction-Based Debug
176(2)
5.6 On-Chip Debug Infrastructure
178(6)
5.6.1 Overview
178(1)
5.6.2 Monitors
178(2)
5.6.3 Computation-Specific Instrument
180(1)
5.6.4 Protocol-Specific Instrument
181(1)
5.6.5 Event Distribution Interconnect
182(1)
5.6.6 Debug Control Interconnect
183(1)
5.6.7 Debug Data Interconnect
183(1)
5.7 Off-Chip Debug Infrastructure
184(6)
5.7.1 Overview
184(1)
5.7.2 Abstractions Used by Debugger Software
184(6)
5.8 Debug Example
190(3)
5.9 Conclusions
193(1)
Review Questions
194(1)
Bibliography
194(7)
6 System-Level Tools for NoC-Based Multi-Core Design 201(42)
Luciano Bononi,
Nicola Concer
Miltos Grammatikakis
6.1 Introduction
202(4)
6.1.1 Related Work
204(2)
6.2 Synthetic Traffic Models
206(1)
6.3 Graph Theoretical Analysis
207(3)
6.3.1 Generating Synthetic Graphs Using TGFF
209(1)
6.4 Task Mapping for SoC Applications
210(6)
6.4.1 Application Task Embedding and Quality Metrics
210(4)
6.4.2 SCOTCH Partitioning Tool
214(2)
6.5 OMNeT++ Simulation Framework
216(1)
6.6 A Case Study
217(14)
6.6.1 Application Task Graphs
217(1)
6.6.2 Prospective NoC Topology Models
218(1)
6.6.3 Spidergon Network on Chip
219(2)
6.6.4 Task Graph Embedding and Analysis
221(2)
6.6.5 Simulation Models for Proposed NoC Topologies
223(4)
6.6.6 Mpeg4: A Realistic Scenario
227(4)
6.7 Conclusions and Extensions
231(3)
Review Questions
234(1)
Bibliography
235(8)
7 Compiler Techniques for Application Level Memory Optimization for MPSoC 243(26)
Bruno Girodias
Youcef Bouchebaba
Pierre Paulin
Bruno Lavigueur
Gabriela Nicolescu
El Mostapha Aboulhamid
7.1 Introduction
244(1)
7.2 Loop Transformation for Single and Multiprocessors
245(1)
7.3 Program Transformation Concepts
246(2)
7.4 Memory Optimization Techniques
248(2)
7.4.1 Loop Fusion
249(1)
7.4.2 Tiling
249(1)
7.4.3 Buffer Allocation
249(1)
7.5 MPSoC Memory Optimization Techniques
250(5)
7.5.1 Loop Fusion
251(1)
7.5.2 Comparison of Lexicographically Positive and Positive Dependency
252(1)
7.5.3 Tiling
253(1)
7.5.4 Buffer Allocation
254(1)
7.6 Technique Impacts
255(1)
7.6.1 Computation Time
255(1)
7.6.2 Code Size Increase
256(1)
7.7 Improvement in Optimization Techniques
256(5)
7.7.1 Parallel Processing Area and Partitioning
256(3)
7.7.2 Modulo Operator Elimination
259(1)
7.7.3 Unimodular Transformation
260(1)
7.8 Case Study
261(2)
7.8.1 Cache Ratio and Memory Space
262(1)
7.8.2 Processing Time and Code Size
263(1)
7.9 Discussion
263(1)
7.10 Conclusions
264(1)
Review Questions
265(1)
Bibliography
266(3)
8 Programming Models for Multi-Core Embedded Software 269(40)
Bijoy A. Jose
Bin Xue
Sandeep K. Shukla
Jean-Pierre Talpin
8.1 Introduction
270(2)
8.2 Thread Libraries for Multi-Threaded Programming
272(4)
8.3 Protections for Data Integrity in a Multi-Threaded Environment
276(3)
8.3.1 Mutual Exclusion Primitives for Deterministic Output
276(2)
8.3.2 Transactional Memory
278(1)
8.4 Programming Models for Shared Memory and Distributed Memory
279(3)
8.4.1 OpenMP
279(1)
8.4.2 Thread Building Blocks
280(1)
8.4.3 Message Passing Interface
281(1)
8.5 Parallel Programming on Multiprocessors
282(1)
8.6 Parallel Programming Using Graphic Processors
283(1)
8.7 Model-Driven Code Generation for Multi-Core Systems
284(2)
8.7.1 StreamIt
285(1)
8.8 Synchronous Programming Languages
286(2)
8.9 Imperative Synchronous Language: Esterel
288(2)
8.9.1 Basic Concepts
288(1)
8.9.2 Multi-Core Implementations and Their Compilation Schemes
289(1)
8.10 Declarative Synchronous Language: LUSTRE
290(2)
8.10.1 Basic Concepts
291(1)
8.10.2 Multi-Core Implementations from LUSTRE Specifications
291(1)
8.11 Multi-Rate Synchronous Language: SIGNAL
292(7)
8.11.1 Basic Concepts
292(1)
8.11.2 Characterization and Compilation of SIGNAL
293(1)
8.11.3 SIGNAL Implementations on Distributed Systems
294(2)
8.11.4 Multi-Threaded Programming Models for SIGNAL
296(3)
8.12 Programming Models for Real-Time Software
299(2)
8.12.1 Real-Time Extensions to Synchronous Languages
300(1)
8.13 Future Directions for Multi-Core Programming
301(1)
Review Questions
302(3)
Bibliography
305(4)
9 Operating System Support for Multi-Core Systems-on-Chips 309(28)
Xavier Guerin
Frederic Petrot
9.1 Introduction
310(1)
9.2 Ideal Software Organization
311(2)
9.3 Programming Challenges
313(1)
9.4 General Approach
314(8)
9.4.1 Board Support Package
314(3)
9.4.2 General Purpose Operating System
317(5)
9.5 Real-Time and Component-Based Operating System Models
322(7)
9.5.1 Automated Application Code Generation and RTOS Modeling
322(4)
9.5.2 Component-Based Operating System
326(3)
9.6 Pros and Cons
329(1)
9.7 Conclusions
330(2)
Review Questions
332(1)
Bibliography
333(4)
10 Autonomous Power Management in Embedded Multi-Cores 337(32)
Arindam Mukherjee
Arun Ravindran
Bharat Kumar Joshi
Kushal Datta
Yue Liu
10.1 Introduction
338(4)
10.1.1 Why Is Autonomous Power Management Necessary?
339(3)
10.2 Survey of Autonomous Power Management Techniques
342(5)
10.2.1 Clock Gating
342(1)
10.2.2 Power Gating
343(1)
10.2.3 Dynamic Voltage and Frequency Scaling
343(1)
10.2.4 Smart Caching
344(1)
10.2.5 Scheduling
345(1)
10.2.6 Commercial Power Management Tools
346(1)
10.3 Power Management and RTOS
347(2)
10.4 Power-Smart RTOS and Processor Simulators
349(2)
10.4.1 Chip Multi-Threading (CMT) Architecture Simulator
350(1)
10.5 Autonomous Power Saving in Multi-Core Processors
351(7)
10.5.1 Opportunities to Save Power
353(1)
10.5.2 Strategies to Save Power
354(2)
10.5.3 Case Study: Power Saving in Intel Centrino
356(2)
10.6 Power Saving Algorithms
358(2)
10.6.1 Local PMU Algorithm
358(1)
10.6.2 Global PMU Algorithm
358(2)
10.7 Conclusions
360(2)
Review Questions
362(1)
Bibliography
363(6)
11 Multi-Core System-on-Chip in Real World Products 369(30)
Gajinder Panesar
Andrew Duller
Alan H. Gray
Daniel Towner
11.1 Introduction
370(1)
11.2 Overview of picoArray Architecture
371(4)
11.2.1 Basic Processor Architecture
371(2)
11.2.2 Communications Interconnect
373(1)
11.2.3 Peripherals and Hardware Functional Accelerators
373(2)
11.3 Tool Flow
375(6)
11.3.1 picoVhdl Parser (Analyzer, Elaborator, Assembler)
376(1)
11.3.2 C Compiler
376(2)
11.3.3 Design Simulation
378(3)
11.3.4 Design Partitioning for Multiple Devices
381(1)
11.3.5 Place and Switch
381(1)
11.3.6 Debugging
381(1)
11.4 picoArray Debug and Analysis
381(7)
11.4.1 Language Features
382(1)
11.4.2 Static Analysis
383(1)
11.4.3 Design Browser
383(2)
11.4.4 Scripting
385(2)
11.4.5 Probes
387(1)
11.4.6 FileIO
387(1)
11.5 Hardening Process in Practice
388(4)
11.5.1 Viterbi Decoder Hardening
389(3)
11.6 Design Example
392(4)
11.7 Conclusions
396(1)
Review Questions
396(1)
Bibliography
397(2)
12 Embedded Multi-Core Processing for Networking 399(66)
Theofanis Orphanoudakis
Stylianos Perissakis
12.1 Introduction
400(3)
12.2 Overview of Proposed NPU Architectures
403(9)
12.2.1 Multi-Core Embedded Systems for Multi-Service Broadband Access and Multimedia Home Networks
403(2)
12.2.2 SoC Integration of Network Components and Examples of Commercial Access NPUs
405(2)
12.2.3 NPU Architectures for Core Network Nodes and High-Speed Networking and Switching
407(5)
12.3 Programmable Packet Processing Engines
412(10)
12.3.1 Parallelism
413(5)
12.3.2 Multi-Threading Support
418(3)
12.3.3 Specialized Instruction Set Architectures
421(1)
12.4 Address Lookup and Packet Classification Engines
422(9)
12.4.1 Classification Techniques
424(2)
12.4.2 Case Studies
426(5)
12.5 Packet Buffering and Queue Management Engines
431(11)
12.5.1 Performance Issues
433(2)
12.5.2 Design of Specialized Core for Implementation of Queue Management in Hardware
435(7)
12.6 Scheduling Engines
442(11)
12.6.1 Data Structures in Scheduling Architectures
443(1)
12.6.2 Task Scheduling
444(6)
12.6.3 Traffic Scheduling
450(3)
12.7 Conclusions
453(2)
Review Questions
455(4)
Bibliography
459(6)
Index 465
Georgios Kornaros is currently with the Applied Informatics and Multimedia Department of the Technological Educational Institute of Crete in Greece and also with the Technical University of Crete, Greece. In the past he worked as a systems architect and designer of single-chip switches and network processor designs for a few research institutes and companies. Kornaros has taped out three single-chip multi-core devices for networking. As a technical manager of the Digital Integrated Systems Group of ISD SA (2000) and later, also as Technical Manager of Ellemedia Technologies Ltd. Crete Department (2001-2005), he designed a few network processors. His research interests include high-speed communication architectures, networking systems, multi-core architectures, embedded and reconfigurable systems, full and semi-custom IC design. Kornaros is the author or co-author of more than 40 publications in refereed international conferences and journals. He is an IEEE member and a member of the Technical Chamber of Greece.