This volume explains models and computer-aided design techniques for the design of nano-scale analog circuits with optimal performances and the links between the physics and technology of scaled MOS (metal-oxide-semiconductor) transistors and the design and simulation of nano-scale analog circuits. It details nano-scale CMOS (complementary metal-oxide-semiconductor) analog technology and general trends of technology scaling in terms of device geometry, process parameters, and supply voltage, as well as challenges involved in analog design and the rationale for computer-aided design techniques; high-level modeling and design techniques; the modeling of a scaled MOS transistor for VLSI (very large scale integration) circuit simulation; performance and feasibility model generation using a learning-based approach and the artificial neural network and least-squares support vector machine method; circuit sizing and specification translation; advanced effects of scaled MOS transistors; and design challenges due to the process variability and reliability of nano-scale CMOS analog circuits. Annotation ©2014 Ringgold, Inc., Portland, OR (protoview.com) Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database.Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physics and technology of scaled MOS transistors and the design and simulation of nano-scale analog circuits. It also explores the development of structured computer-aided design (CAD) techniques for architecture-level and circuit-level design of analog circuits.The book outlines the general trends of technology scaling with respect to device geometry, process parameters, and supply voltage. It describes models and optimization techniques, as well as the compact modeling of scaled MOS transistors for VLSI circuit simulation. • Includes two learning-based methods: the artificial neural network (ANN) and the least-squares support vector machine (LS-SVM) method• Provides case studies demonstrating the practical use of these two methods• Explores circuit sizing and specification translation tasks• Introduces the particle swarm optimization technique and provides examples of sizing analog circuits• Discusses the advanced effects of scaled MOS transistors like narrow width effects, and vertical and lateral channel engineeringNano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design describes the models and CAD techniques, explores the physics of MOS transistors, and considers the design challenges involving statistical variations of process technology parameters and reliability constraints related to circuit design.
Arvustused
" for appropriate usage of CAD tools, deep understanding of various models and methodologies are needed for the success of todays IC design. [ this book] addresses such needs for IC design in general and analog design in particular. Thus, this is a very valuable book for students and practicing engineers involved in microelectronics." Dr. Samar K. Saha, Adjunct Prof. Santa Clara University; VP of Publications, IEEE Electron Devices Society
Introduction. High-Level Modeling and Design Techniques. Modeling of
Scaled MOS Transistor for VLSI Circuit Simulation. Performance and
Feasibility Model Generation using Learning based Approach. Circuit Sizing
and Specification Translation. Advanced Effects of Scaled MOS Transistors.
Process Variability and Reliability of Nano-scale CMOS Analog Circuits.
Bibliography.
Soumya Pandit received a B.Sc degree with Physics Honors, M.Sc degree in electronic science from University of Calcutta in 1998 and 2000, and an M.Tech degree in radio physics and electronics from the same university in 2002. He obtained his PhD degree from Indian Institute of Technology, Kharagpur in information technology in the year 2009. His current research activities are on statistical CMOS analog circuit design and optimization, process-device-circuit interaction, and soft computing applications. Dr. Pandit has to his credit several international journal and conference publications. He is a member of IEEE, USA and an associate member of the Institute of Engineers (India).
Chittaranjan Mandal
received his PhD from the Indian Institute of Technology, Kharagpur, India, in 1997. He is currently a professor in the Department of Computer Science and Engineering and also the School of Information Technology at IIT, Kharagpur. His research interests include high-level system design, formal modeling, and verification. He has been an Industrial Fellow of Kingston University, UK, since 2000 and was also a recipient of a Royal Society Fellowship for conducting collaborative research in the UK. He has handled sponsored projects from government agencies as well as private agencies such as Nokia, Natsem, and Intel. He also serves as a reviewer for several journals and conferences.
Amit Patra
received B.Tech., M.Tech., and Ph.D. degrees from the Indian Institute of Technology, Kharagpur in 1984, 1986, and 1990 respectively. He is currently a professor of electrical engineering at IIT Kharagpur where he served as the Dean (Alumni Affairs and International Relations) between 2007 and 2013. His current research interests include power management circuits, mixed-signal SoC design and embedded control systems. He has published more than 200 research papers and designed about 12 integrated circuits. He has carried out sponsored research with multiple industries such as National Semiconductor Corporation, Freescale Semiconductor, Infineon Technologies and Maxim Integrated Circuits.
