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Nanoscale Memory Repair [Kõva köide]

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  • Formaat: Hardback, 218 pages, kõrgus x laius: 235x155 mm, kaal: 1100 g, X, 218 p., 1 Hardback
  • Sari: Integrated Circuits and Systems
  • Ilmumisaeg: 13-Jan-2011
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1441979573
  • ISBN-13: 9781441979575
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Nanoscale Memory RepairSuurem pilt
  • Formaat: Hardback, 218 pages, kõrgus x laius: 235x155 mm, kaal: 1100 g, X, 218 p., 1 Hardback
  • Sari: Integrated Circuits and Systems
  • Ilmumisaeg: 13-Jan-2011
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1441979573
  • ISBN-13: 9781441979575
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781441979575.html
Märksõnad:
Written from years of experience with developing memories and low-voltage CMOS circuits, Nanoscale Memory Repair describes yield and reliability issues in terms of mathematics and engineering. Readers will find a detailed explanation of the various yield models and calculations.

Yield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. This book systematically describes these yield and reliability issues in terms of mathematics and engineering, as well as an array of repair techniques, based on the authors' long careers in developing memories and low-voltage CMOS circuits. Nanoscale Memory Repair gives a detailed explanation of the various yield models and calculations, as well as various, practical logic and circuits that are critical for higher yield and reliability.
1 An Introduction to Repair Techniques
1(18)
1.1 Introduction
1(1)
1.2 Hard and Soft Errors and Repair Techniques
1(8)
1.2.1 Hard and Soft Errors
2(1)
1.2.2 Redundancy
3(2)
1.2.3 ECC
5(3)
1.2.4 Combination of Redundancy and ECC
8(1)
1.2.5 Others
8(1)
1.3 Margin Errors and Repair Techniques
9(6)
1.3.1 Device and Process Variations
11(1)
1.3.2 Timing and Voltage Margin Errors
11(3)
1.3.3 Reductions of Margin Errors
14(1)
1.4 Speed-Relevant Errors and Repair Techniques
15(1)
References
16(3)
2 Redundancy
19(50)
2.1 Introduction
19(1)
2.2 Models of Fault Distribution
20(5)
2.2.1 Poisson Distribution Model
20(2)
2.2.2 Negative-Binomial Distribution Model
22(3)
2.3 Yield Improvement Through Redundancy
25(4)
2.4 Replacement Schemes
29(7)
2.4.1 Principle of Replacement
29(1)
2.4.2 Circuit Implementations
30(6)
2.5 Intrasubarray Replacement
36(16)
2.5.1 Simultaneous and Individual Replacement
39(3)
2.5.2 Flexible Replacement
42(7)
2.5.3 Variations of Intrasubarray Replacement
49(3)
2.6 Intersubarray Replacement
52(2)
2.7 Subarray Replacement
54(2)
2.8 Devices for Storing Addresses
56(5)
2.8.1 Fuses
56(2)
2.8.2 Antifuses
58(2)
2.8.3 Nonvolatile Memory Cells
60(1)
2.9 Testing for Redundancy
61(3)
References
64(5)
3 Error Checking and Correction (ECC)
69(70)
3.1 Introduction
69(1)
3.2 Linear Algebra and Linear Codes
70(5)
3.2.1 Coding Procedure
70(2)
3.2.2 Decoding Procedure
72(3)
3.3 Galois Field
75(2)
3.4 Error-Correcting Codes
77(15)
3.4.1 Minimum Distance
78(1)
3.4.2 Number of Check Bits
79(3)
3.4.3 Single Parity Check Code
82(1)
3.4.4 Hamming Code
82(2)
3.4.5 Extended Hamming Code and Hsiao Code
84(1)
3.4.6 Bidirectional Parity Code
85(1)
3.4.7 Cyclic Code
86(3)
3.4.8 Nonbinary Code
89(3)
3.5 Coding and Decoding Circuits
92(13)
3.5.1 Coding and Decoding Circuits for Hamming Code
92(5)
3.5.2 Coding and Decoding Circuits for Cyclic Hamming Code
97(5)
3.5.3 Coding and Decoding Circuits for Nonbinary Code
102(3)
3.6 Theoretical Reduction in Soft-Error and Hard-Error Rates
105(6)
3.6.1 Reduction in Soft-Error Rate
105(3)
3.6.2 Reduction in Hard-Error Rate
108(3)
3.7 Application of ECC
111(24)
3.7.1 Application to Random-Access Memories
112(14)
3.7.2 Application to Serial-Access Memories
126(4)
3.7.3 Application to Multilevel-Storage Memories
130(3)
3.7.4 Application to Other Memories
133(2)
3.8 Testing for ECC
135(1)
References
136(3)
4 Combination of Redundancy and Error Correction
139(18)
4.1 Introduction
139(1)
4.2 Repair of Bit Faults Using Synergistic Effect
139(10)
4.2.1 Principle of Synergistic Effect
139(5)
4.2.2 Yield Estimation
144(5)
4.3 Application of Synergistic Effect
149(6)
4.3.1 Threshold-Voltage Variations
149(2)
4.3.2 Estimated Effect
151(4)
References
155(2)
5 Reduction Techniques for Margin Errors of Nanoscale Memories
157(46)
5.1 Introduction
157(2)
5.2 Definition of Vmin
159(1)
5.3 Reduction of Vmin for Wider Margins
160(5)
5.3.1 General Features of Vmin
160(5)
5.3.2 Comparison of Vmin for Logic Block, SRAMs, and DRAMs
165(1)
5.4 Advanced MOSFETs for Wider Margins
165(8)
5.4.1 Planar FD-SOI MOSFETs
167(2)
5.4.2 FinFETs
169(4)
5.5 Logic Circuits for Wider Margins
173(9)
5.5.1 Gate-Source Offset Driving
174(4)
5.5.2 Gate-Source Differential Driving
178(2)
5.5.3 Combined Driving
180(1)
5.5.4 Instantaneous Activation of Low-Vt0 MOSFETs
181(1)
5.5.5 Gate Boosting of High-Vt0 MOSFETs
181(1)
5.6 SRAMs for Wider Margins
182(6)
5.6.1 Ratio Operations of the 6-T Cell
182(1)
5.6.2 Shortening of Datalines and Up-Sizing of the 6-T Cell
183(2)
5.6.3 Power Managements of the 6-T Cell
185(2)
5.6.4 The 8-T Cell
187(1)
5.7 DRAMs for Wider Margins
188(6)
5.7.1 Sensing Schemes
188(1)
5.7.2 Vmin(SA) of Sense Amplifier
189(1)
5.7.3 Vmin(Cell) of Cell
190(1)
5.7.4 Comparison Between Vmin(SA) and Vmin(Cell)
190(1)
5.7.5 Low-Vt0 Sense Amplifier
191(1)
5.7.6 FD-SOI Cells
192(2)
5.8 Subsystems for Wider Margins
194(4)
5.8.1 Improvement of Power Supply Integrity
194(1)
5.8.2 Reduction in Vt0 at Subsystem Level
195(1)
5.8.3 Low-Vt0 Power Switches
196(2)
References
198(5)
6 Reduction Techniques for Speed-Relevant Errors of Nanoscale Memories
203(10)
6.1 Introduction
203(1)
6.2 Reduction Techniques for Speed-Degradation Errors
204(1)
6.3 Reduction Techniques for Interdie Speed-Variation Errors
205(7)
6.3.1 On-Chip VBB Compensation
207(4)
6.3.2 On-Chip VDD Compensation and Others
211(1)
References
212(1)
Index 213