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Network-on-Chip: The Next Generation of System-on-Chip Integration [Kõva köide]

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, (Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, West Bengal, India)
  • Formaat: Hardback, 388 pages, kõrgus x laius: 234x156 mm, kaal: 660 g, 50 Tables, black and white; 194 Illustrations, black and white
  • Ilmumisaeg: 15-Dec-2014
  • Kirjastus: CRC Press Inc
  • ISBN-10: 1466565268
  • ISBN-13: 9781466565265
Teised raamatud teemal:
Network-on-Chip: The Next Generation of System-on-Chip IntegrationSuurem pilt
  • Formaat: Hardback, 388 pages, kõrgus x laius: 234x156 mm, kaal: 660 g, 50 Tables, black and white; 194 Illustrations, black and white
  • Ilmumisaeg: 15-Dec-2014
  • Kirjastus: CRC Press Inc
  • ISBN-10: 1466565268
  • ISBN-13: 9781466565265
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781466565265.html
Märksõnad:
Kundu and Chattopadhyay present students, academics, and researchers with an investigation of network-on-chip integration. The authors have organized the main body of their text into twelve chapters, focused on interconnection networks in network-on-chip, architecture design of network-on-chip, evaluation of network-on-chip architecture, application mapping on network-on-chip, low-power techniques for network-on-chip, signal integrity and reliability of network-on-chip, and a variety of other related subjects. Santanu Kundu is a system-on-chip senior design engineer in India. Santanu Chattopadhyay is a faculty member of the Indian Institute of Technology. Annotation ©2015 Ringgold, Inc., Portland, OR (protoview.com) Addresses the Challenges Associated with System-on-Chip IntegrationNetwork-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challengesNoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfacesThe router design strategies followed in NoCsThe evaluation mechanism of NoC architecturesThe application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCsThe signal integrity and reliability issues of NoCThe details of NoC testing strategies reported so farThe problem of synthesizing application-specific NoCsReconfigurable NoC design issuesDirection of future research and development in the field of NoCNetwork-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.

Arvustused

"What makes this book special as compared to the current literature in the field is that it provides a complete picture of NoC architectures. In fact, current books in the context of NoCs are usually specific and presuppose a basic knowledge of NoC architectures. Conversely, this book provides a complete guide for both unskilled readers and researchers working in the area, to acquire not only the basic concepts but also the advanced techniques for improving power, cost and performance metrics of the on-chip communication system." Maurizio Palesi, Kore University, Italy

Preface xiii
Authors xvii
1 Introduction
1(12)
1.1 System-on-Chip Integration and Its Challenges
1(2)
1.2 SoC to Network-on-Chip: A Paradigm Shift
3(2)
1.3 Research Issues in NoC Development
5(3)
1.4 Existing NoC Examples
8(2)
1.5 Summary
10(3)
References
10(3)
2 Interconnection Networks in Network-on-Chip
13(40)
2.1 Introduction
13(1)
2.2 Network Topologies
14(15)
2.2.1 Number of Edges
25(1)
2.2.2 Average Distance
25(4)
2.3 Switching Techniques
29(1)
2.4 Routing Strategies
30(13)
2.4.1 Routing-Dependent Deadlock
31(2)
2.4.1.1 Deterministic Routing in M × N MoT Network
33(8)
2.4.2 Avoidance of Message-Dependent Deadlock
41(2)
2.5 Flow Control Protocol
43(2)
2.6 Quality-of-Service Support
45(1)
2.7 NI Module
46(2)
2.8 Summary
48(5)
References
48(5)
3 Architecture Design of Network-on-Chip
53(22)
3.1 Introduction
53(1)
3.2 Switching Techniques and Packet Format
53(1)
3.3 Asynchronous FIFO Design
54(3)
3.4 GALS Style of Communication
57(1)
3.5 Wormhole Router Architecture Design
57(6)
3.5.1 Input Channel Module
58(1)
3.5.2 Output Channel Module
58(5)
3.6 VC Router Architecture Design
63(7)
3.6.1 Input Channel Module
65(1)
3.6.2 Output Links
66(1)
3.6.2.1 VC Allocator
66(3)
3.6.2.2 Switch Allocator
69(1)
3.7 Adaptive Router Architecture Design
70(3)
3.8 Summary
73(2)
References
73(2)
4 Evaluation of Network-on-Chip Architectures
75(44)
4.1 Evaluation Methodologies of NoC
75(6)
4.1.1 Performance Metrics
78(2)
4.1.2 Cost Metrics
80(1)
4.2 Traffic Modeling
81(3)
4.3 Selection of Channel Width and Flit Size
84(1)
4.4 Simulation Results and Analysis of MoT Network with WH Router
84(6)
4.4.1 Accepted Traffic versus Offered Load
85(1)
4.4.2 Throughput versus Locality Factor
85(1)
4.4.3 Average Overall Latency at Different Locality Factors
86(2)
4.4.4 Energy Consumption at Different Locality Factors
88(2)
4.5 Impact of FIFO Size and Placement in Energy and Performance of a Network
90(3)
4.6 Performance and Cost Comparison of MoT with Other NoC Structures Having WH Router under Self-Similar Traffic
93(10)
4.6.1 Network Area Estimation
94(2)
4.6.2 Network Aspect Ratio
96(1)
4.6.3 Performance Comparison
97(1)
4.6.3.1 Accepted Traffic versus Offered Load
97(1)
4.6.3.2 Throughput versus Locality Factor
98(1)
4.6.3.3 Average Overall Latency under Localized Traffic
99(3)
4.6.4 Comparison of Energy Consumption
102(1)
4.7 Simulation Results and Analysis of MoT Network with Virtual Channel Router
103(6)
4.7.1 Throughput versus Offered Load
104(1)
4.7.2 Latency versus Offered Load
104(1)
4.7.3 Energy Consumption
105(3)
4.7.4 Area Required
108(1)
4.8 Performance and Cost Comparison of MoT with Other NoC Structures Having VC Router
109(5)
4.8.1 Accepted Traffic versus Offered Load
109(1)
4.8.2 Throughput versus Locality Factor
109(1)
4.8.3 Average Overall Latency under Localized Traffic
110(1)
4.8.4 Energy Consumption
111(2)
4.8.5 Area Overhead
113(1)
4.9 Limitations of Tree-Based Topologies
114(1)
4.10 Summary
115(4)
References
116(3)
5 Application Mapping on Network-on-Chip
119(36)
5.1 Introduction
119(1)
5.2 Mapping Problem
120(3)
5.3 ILP Formulation
123(5)
5.3.1 Other ILP Formulations
127(1)
5.4 Constructive Heuristics for Application Mapping
128(6)
5.4.1 Binomial Merging Iteration
130(1)
5.4.2 Topology Mapping and Traffic Surface Creation
131(1)
5.4.3 Hardware Cost Optimization
132(2)
5.5 Constructive Heuristics with Iterative Improvement
134(7)
5.5.1 Initialization Phase
134(1)
5.5.2 Shortest Path Computation
135(1)
5.5.3 Iterative Improvement Phase
136(1)
5.5.4 Other Constructive Strategies
137(4)
5.6 Mapping Using Discrete PSO
141(9)
5.6.1 Particle Structure
141(1)
5.6.2 Evolution of Generations
142(1)
5.6.3 Convergence of DPSO
143(1)
5.6.4 Overall PSO Algorithm
144(1)
5.6.5 Augmentations to the DPSO
144(1)
5.6.5.1 Multiple PSO
144(1)
5.6.5.2 Initial Population Generation
145(3)
5.6.6 Other Evolutionary Approaches
148(2)
5.7 Summary
150(5)
References
150(5)
6 Low-Power Techniques for Network-on-Chip
155(36)
6.1 Introduction
155(3)
6.2 Standard Low-Power Methods for NoC Routers
158(8)
6.2.1 Clock Gating
158(1)
6.2.2 Gate Level Power Optimization
159(1)
6.2.3 Multivoltage Design
160(1)
6.2.3.1 Challenges in Multivoltage Design
161(3)
6.2.4 Multi-VT Design
164(1)
6.2.5 Power Gating
165(1)
6.3 Standard Low-Power Methods for NoC Links
166(6)
6.3.1 Bus Energy Model
167(1)
6.3.2 Low-Power Coding
168(2)
6.3.3 On-Chip Serialization
170(1)
6.3.4 Low-Swing Signaling
171(1)
6.4 System-Level Power Reduction
172(16)
6.4.1 Dynamic Voltage Scaling
172(2)
6.4.1.1 History-Based DVS
174(4)
6.4.1.2 Hardware Implementation
178(1)
6.4.1.3 Results and Discussions
179(1)
6.4.2 Dynamic Frequency Scaling
179(2)
6.4.2.1 History-Based DFS
181(2)
6.4.2.2 DFS Algorithm
183(1)
6.4.2.3 Link Controller
183(1)
6.4.2.4 Results and Discussions
184(1)
6.4.3 VFI Partitioning
185(1)
6.4.4 Runtime Power Gating
186(2)
6.5 Summary
188(3)
References
188(3)
7 Signal Integrity and Reliability of Network-on-Chip
191(44)
7.1 Introduction
191(2)
7.2 Sources of Faults in NoC Fabric
193(11)
7.2.1 Permanent Faults
194(1)
7.2.2 Faults due to Aging Effects
194(1)
7.2.2.1 Negative-Bias Temperature Instability
194(1)
7.2.2.2 Hot Carrier Injection
195(1)
7.2.3 Transient Faults
195(1)
7.2.3.1 Capacitive Crosstalk
195(4)
7.2.3.2 Soft Errors
199(4)
7.2.3.3 Some Other Sources of Transient Faults
203(1)
7.3 Permanent Fault Controlling Techniques
204(1)
7.4 Transient Fault Controlling Techniques
205(16)
7.4.1 Intra-Router Error Control
205(1)
7.4.1.1 Soft Error Correction
206(4)
7.4.2 Inter-Router Link Error Control
210(1)
7.4.2.1 Capacitive Crosstalk Avoidance Techniques
210(6)
7.4.2.2 Error Detection and Retransmission
216(4)
7.4.2.3 Error Correction
220(1)
7.5 Unified Coding Framework
221(6)
7.5.1 Joint CAC and LPC Scheme (CAC + LPC)
222(1)
7.5.2 Joint LPC and ECC Scheme (LPC + ECC)
223(1)
7.5.3 Joint CAC and ECC Scheme (CAC + ECC)
224(3)
7.5.4 Joint CAC, LPC, and ECC Scheme (CAC + LPC + ECC)
227(1)
7.6 Energy and Reliability Trade-Off in Coding Technique
227(3)
7.7 Summary
230(5)
References
231(4)
8 Testing of Network-on-Chip Architectures
235(28)
8.1 Introduction
235(1)
8.2 Testing Communication Fabric
236(9)
8.2.1 Testing NoC Links
237(1)
8.2.2 Testing NoC Switches
238(1)
8.2.3 Test Data Transport
239(2)
8.2.4 Test Transport Time Minimization---A Graph Theoretic Formulation
241(1)
8.2.4.1 Unicast Test Scheduling
242(2)
8.2.4.2 Multicast Test Scheduling
244(1)
8.3 Testing Cores
245(15)
8.3.1 Core Wrapper Design
246(4)
8.3.2 ILP Formulation
250(3)
8.3.3 Heuristic Algorithms
253(5)
8.3.4 PSO-Based Strategy
258(1)
8.3.4.1 Particle Structure and Fitness
258(1)
8.3.4.2 Evolution of Generations
259(1)
8.4 Summary
260(3)
References
260(3)
9 Application-Specific Network-on-Chip Synthesis
263(26)
9.1 Introduction
263(1)
9.2 ASNoC Synthesis Problem
264(1)
9.3 Literature Survey
265(3)
9.4 System-Level Floorplanning
268(3)
9.4.1 Variables
268(1)
9.4.1.1 Independent Variables
268(1)
9.4.1.2 Dependent Variables
268(1)
9.4.2 Objective Function
269(1)
9.4.3 Constraints
269(1)
9.4.4 Constraints for Mesh Topology
270(1)
9.5 Custom Interconnection Topology and Route Generation
271(6)
9.5.1 Variables
272(1)
9.5.1.1 Independent Variables
272(1)
9.5.1.2 Derived Variables
273(1)
9.5.2 Objective Function
273(1)
9.5.3 Constraints
274(3)
9.6 ASNoC Synthesis with Flexible Router Placement
277(7)
9.6.1 ILP for Flexible Router Placement
278(1)
9.6.1.1 Variables
278(1)
9.6.1.2 Objective Function
279(1)
9.6.1.3 Constraints
279(2)
9.6.2 PSO for Flexible Router Placement
281(1)
9.6.2.1 Particle Structure and Fitness Function
282(1)
9.6.2.2 Local and Global Bests
282(1)
9.6.2.3 Evolution of Generation
283(1)
9.6.2.4 Swap Operator
283(1)
9.6.2.5 Swap Sequence
283(1)
9.7 Summary
284(5)
References
284(5)
10 Reconfigurable Network-on-Chip Design
289(28)
10.1 Introduction
289(1)
10.2 Literature Review
290(1)
10.3 Local Reconfiguration Approach
291(13)
10.3.1 Routers
292(1)
10.3.2 Multiplexers
293(1)
10.3.3 Selection Logic
294(1)
10.3.4 Area Overhead
294(2)
10.3.5 Design Flow
296(2)
10.3.5.1 Construction of CCG
298(1)
10.3.5.2 Mapping of CCG
299(1)
10.3.5.3 Configuration Generation
299(1)
10.3.6 ILP-Based Approach
299(1)
10.3.6.1 Parameters and Variables
300(1)
10.3.6.2 Objective Function
300(1)
10.3.6.3 Constraints
300(1)
10.3.7 PSO Formulation
301(1)
10.3.7.1 Particle Formulation and Fitness Function
302(1)
10.3.8 Iterative Reconfiguration
303(1)
10.4 Topology Reconfiguration
304(7)
10.4.1 Modification around Routers
305(1)
10.4.2 Reconfiguration Architecture
306(1)
10.4.2.1 Application Mapping
307(2)
10.4.2.2 Core-to-Network Mapping
309(1)
10.4.2.3 Topology and Route Generation
310(1)
10.5 Link Reconfiguration
311(1)
10.5.1 Estimating Channel Bandwidth Utilization
311(1)
10.6 Summary
312(5)
References
314(3)
11 Three-Dimensional Integration of Network-on-Chip
317(36)
11.1 Introduction
317(1)
11.2 3D Integration: Pros and Cons
318(5)
11.2.1 Opportunities of 3D Integration
319(2)
11.2.2 Challenges of 3D Integration
321(2)
11.3 Design and Evaluation of 3D NoC Architecture
323(27)
11.3.1 3D Mesh-of-Tree Topology
326(1)
11.3.1.1 Number of Directed Edges
326(1)
11.3.1.2 Average Distance
327(4)
11.3.2 Performance and Cost Evaluation
331(5)
11.3.2.1 Network Area Estimation
336(3)
11.3.2.2 Network Aspect Ratio
339(1)
11.3.3 Simulation Results with Self-Similar Traffic
340(1)
11.3.3.1 Accepted Traffic versus Offered Load
340(1)
11.3.3.2 Throughput versus Locality Factor
341(1)
11.3.3.3 Average Overall Latency under Localized Traffic
342(3)
11.3.3.4 Energy Consumption
345(4)
11.3.4 Simulation Results with Application-Specific Traffic
349(1)
11.4 Summary
350(3)
References
351(2)
12 Conclusions and Future Trends
353(6)
12.1 Conclusions
353(1)
12.2 Future Trends
354(1)
12.2.1 Photonic NoC
354(1)
12.2.2 Wireless NoC
354(1)
12.3 Comparison between Alternatives
355(4)
References
357(2)
Index 359
Santanu Kundu received his BTech in instrumentation engineering from Vidyasagar University, Medinipur, West Bengal, India, in 2002. He received his MTech in instrumentation and electronics engineering from Jadavpur University, Kolkata, West Bengal, India, in 2006. Immediately after that he joined the electronics and electrical communication engineering department at the Indian Institute of Technology, Kharagpur, West Bengal, India. He received his PhD in 2011. His research interests include network-on-chip architecture design in 2D and 3D environments, performance and cost evaluation, signal integrity in nanometer regime, fault-tolerant schemes, and powerperformancereliability trade-off. He is currently a system-on-chip (SoC) design engineer at LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India.







Santanu Chattopadhyay

received his BE in computer science and technology from Calcutta University (BE College), Kolkata, West Bengal, in 1990. In 1992 and 1996, he received his MTech in computer and information technology and PhD in computer science and engineering, respectively, both from the Indian Institute of Technology (IIT), Kharagpur, West Bengal, India. He is currently a professor in the electronics and electrical communication engineering department at the IIT, Kharagpur. He has contributed to more than 100 publications in refereed international journals and conferences. He has also coauthored and written several textbooks, and is a member of the editorial board of the journal IET Circuits, Devices and Systems.