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Network Processor Design: Issues and Practices [Pehme köide]

(Washington University, St. Louis), (Integrated Device Technology, Inc.), (Associate Professor, Computer Science & Engineering, Washington University in St. Louis), (Polytechnic University, New York)
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As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS.


Network processor design is an emerging field with issues and opportunities both numerous and formidable. To help meet this challenge, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. In addition to including the results of the Workshop in this volume, the editors also present specially commissioned material from practicing designers, who discuss their companies' latest network processors. Network Processor Design: Issues and Practices is an essential reference on network processors for graduate students, researchers, and practicing designers.

* Includes contributions from major academic and industrial research labs including Aachen University of Technology; Cisco Systems; Infineon Technologies; Intel Corp.; North Carolina State University; Swiss Federal Institute of Technology; University of California, Berkeley; University of Dortmund; University of Washington; and Washington University.
* Examines the latest network processors from Agere Systems, Cisco, IBM, Intel, Motorola, Sierra Inc., and TranSwitch.


As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS.


Network processor design is an emerging field with issues and opportunities both numerous and formidable. To help meet this challenge, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. In addition to including the results of the Workshop in this volume, the editors also present specially commissioned material from practicing designers, who discuss their companies' latest network processors. Network Processor Design: Issues and Practices is an essential reference on network processors for graduate students, researchers, and practicing designers.

* Includes contributions from major academic and industrial research labs including Aachen University of Technology; Cisco Systems; Infineon Technologies; Intel Corp.; North Carolina State University; Swiss Federal Institute of Technology; University of California, Berkeley; University of Dortmund; University of Washington; and Washington University.
* Examines the latest network processors from Agere Systems, Cisco, IBM, Intel, Motorola, Sierra Inc., and TranSwitch.

Arvustused

"Highly recommended for practitioner and researcher alike, Network Processor Design introduces an important group of commercial and proprietary network processors and covers the latest thinking in the design and use of this important new class of application-specific processors." --John F. Wakerly, Consulting Professor, Stanford University

Muu info

* Includes contributions from major academic and industrial research labs including Aachen University of Technology; Cisco Systems; Infineon Technologies; Intel Corp.; North Carolina State University; Swiss Federal Institute of Technology; University of California, Berkeley; University of Dortmund; University of Washington; and Washington University. * Examines the latest network processors from Agere Systems, Cisco, IBM, Intel, Motorola, Sierra Inc., and TranSwitch.
Preface xiii
Network Processors: An Introduction to Design Issues
1(8)
Patrick Crowley
Mark A. Franklin
Haldun Hadimioglu
Peter F. Onufryk
Design Challenges
3(1)
Design Techniques
4(3)
Challenges and Conclusions
7(2)
PART I DESIGN PRINCIPLES 9(180)
Benchmarking Network Processors
11(16)
Prashant R. Chandra
Frank Hady
Raj Yavatkar
Tony Bock
Mason Cabot
Philip Mathew
Benchmarking Framework Overview
12(3)
Hardware-Level Benchmarks
15(3)
Microlevel Benchmarks
18(3)
Function-Level Benchmarks
21(2)
Related Work
23(4)
References
24(3)
A Methodology and Simulator for the Study of Network Processors
27(28)
Deepak Suryanarayanan
John Marshall
Gregory T. Byrd
Previous Work
28(2)
Component Network Simulator (ComNetSim)
30(2)
The Cisco Toaster2
32(3)
Implementation of ComNetSim
35(9)
Application Development
44(4)
Organization and Configuration
48(1)
Experiments and Results
48(4)
Conclusion and Future Work
52(3)
References
53(2)
Design Space Exploration of Network Processor Architectures
55(36)
Lothar Thiele
Samarjit Chakraborty
Matthias Gries
Simon Kunzli
Models for Streams, Tasks, and Resources
58(5)
Analysis Using a Scheduling Network
63(16)
Multiobjective Design Space Exploration
79(2)
Case Study
81(10)
Acknowledgments
86(1)
References
87(4)
Compiler Backend Optimizations for Network Processors with Bit Packet Addressing
91(26)
Jens Wagner
Rainer Leupers
Bit-Level Data Flow Analysis and Bit Value Inference
95(4)
Code Selection
99(7)
Register Allocation Considering Register Arrays
106(3)
Dead Code Elimination
109(1)
Implementation
110(2)
Results
112(5)
Acknowledgments
113(1)
References
113(4)
A Network Processor Performance and Design Model with Benchmark Parameterization
117(24)
Mark A. Franklin
Tilman Wolf
The Performance Model
119(7)
Workload and System Characteristics
126(4)
Design Results
130(8)
Conclusion
138(3)
References
138(3)
A Benchmarking Methodology for Network Processors
141(26)
Mel Tsai
Chidamber Kulkarni
Niraj Shah
Kurt Keutzer
Christian Sauer
Related Work
143(3)
A Benchmarking Methodology
146(12)
The Benchmark Suite
158(2)
Preliminary Results
160(3)
Conclusion and Future Work
163(4)
References
164(3)
A Modeling Framework for Network Processor Systems
167(22)
Patrick Crowley
Jean-Loup Baer
Framework Description
168(9)
System Modeling
177(7)
IPSec VPN Decryption
184(2)
Packet Size Distributions
186(1)
Conclusion and Future Work
187(2)
Acknowledgments
187(1)
References
187(2)
PART II PRACTICES 189(130)
An Industry Analyst's Perspective on Network Processors
191(28)
John Freeman
History of Packet Processing
191(8)
The Need for Programmability
199(4)
Network Processors
203(2)
Where Do NPs Fit in a System?
205(4)
Evaluating NP Solutions
209(6)
Trends
215(4)
Agere Systems---Communications Optimized PayloadPlus Network Processor Architecture
219(16)
Bill Klein
Juan Garza
Target Applications
220(1)
PayloadPlus Optimized Pipeline-Based Hardware Architecture
220(5)
3G/Media Gateway Application Example
225(1)
FPP Details
225(3)
RSP details
228(2)
Software Architecture and Overview
230(2)
Agere Performance Benefits at OC-48c
232(3)
References
233(2)
Cisco Systems---Toaster2
235(14)
John Marshall
Target Application(s)
235(3)
Packet Flow Example for a Centralized System
238(1)
Packet Flow Example for a Distributed System
239(1)
Toaster2 Hardware Architecture
240(1)
External Memory Controller
241(1)
Internal Column Memory
241(1)
Input and Output Header Buffers
241(1)
Toaster MicroController
242(3)
Tag Buffer
245(1)
Route Processor interface
245(1)
Lock Controller
245(1)
Software Architecture
246(1)
Toaster Development Methodology and Environment
246(1)
Performance Claims
247(1)
Family of Toaster Network Processors
248(1)
Conclusion
248(1)
IBM---PowerNP Network Processor
249(10)
Mohammad Peyravian
Jean Calvignac
Ravi Sabhikhi
Hardware Architecture
251(4)
Software
255(2)
Performance
257(1)
Conclusion
258(1)
Acknowledgments
258(1)
References
258(1)
Intel Corporation---Intel IXP2400 Network Processor: A Second-Generation Intel NPU
259(18)
Prashant Chandra
Sridhar Lakshmanamurthy
Raj Yavatkar
Target Applications
259(1)
Hardware Architecture
260(6)
Software Development Environment
266(7)
IXP2400 System Configurations and Performance Analysis
273(1)
Conclusion
274(3)
References
275(2)
Motorola---C-5e Network Processor
277(14)
Eran Cohen Strod
Patricia Johnson
Target Applications
278(2)
Hardware Architecture
280(7)
Software Architecture
287(3)
Conclusion
290(1)
References
290(1)
PMC-Sierra, Inc.---ClassiPI
291(16)
Vineet Dujari
Remby Taas
Ajit Shelat
Target Applications
291(3)
ClassiPI Architecture
294(1)
System Interface (SI)
295(1)
Field Extraction Engine (FEE)
295(1)
Classification Engine (CE)
295(2)
External RAM (ERAM) Interface
297(1)
ClassiPI Control and Sequencer Block
297(1)
Cascade Interface
298(1)
ClassiPI Implementation
299(1)
Software Architecture and Development Kit
299(1)
Platforms
299(1)
Modules
300(1)
Software Development
300(1)
Simulator
301(1)
Debugger
301(1)
ClassiPI Application Example: A Complex Security-Enabled Router
302(2)
Performance
304(1)
Conclusion
304(3)
References
305(2)
TranSwitch---ASPEN: Flexible Network Processing for Access Solutions
307(12)
Subhash C. Roy
Applications
307(3)
ASPEN Operation and Architecture
310(6)
Programming Environment
316(1)
Conclusion
317(2)
References
318(1)
Index 319(18)
About the Editors 337


Mark A. Franklin received his B.A., B.S.E.E. and M.S.E.E. from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently at Washington University in St. Louis where he has a joint appointment in Electrical Engineering and Computer Science, and holds the Urbauer Chair in Engineering. He founded and is Director of the Computer and Communications Research Center and until recently was the Director of the Undergraduate Program in Computer Engineering. Dr. Franklin is engaged in research, teaching and consulting in the areas of computer and communications architectures, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation. He is a Fellow of the IEEE, a member of the ACM, and has been an organizer and reviewer for numerous professional conferences including the HPCA8 Workshop on Network Processors (2002). He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chairman of the ACM SIGARCH (Special Interest Group on Computer Architecture). Patrick Crowley is an associate Professor in the Department of Computer Science & Engineering at Washington University in St. Louis, Missouri. His research interests are in computer and network systems architecture, with a current focus on the design of programmable embedded network systems and the invention of superior network monitoring and security techniques. He co-founded the ACM/IEEE Symposium on Architectures for Networking and Communications Systems, and co-edited the three-book series, Network Processor Design. He serves as Associate Editor of the IEEE/ACM Transactions on Networking. In 2007, Crowley was chosen to join the DARPA Computer Science Study Group. Haldun Hadimioglu received his BS and MS degrees in Electrical Engineering at Middle East Technical University, Ankara Turkey and his Ph.D. in Computer Science from Polytechnic University in New York. He is currently an Industry Associate Professor in the Computer Science Department and a member of the Computer Engineering faculty at the Polytechnic University. He worked as a research engineer at PETAS, Ankara Turkey (1980-1982). Dr. Hadimioglu's research and teaching interests include Computer Architecture, Parallel and Distributed Systems, Networking and VLSI Design. He was a guest editor of the special issue on "Advances in High Performance Memory Systems," IEEE Transactions on Computers (Nov 2001) and has reviewed papers for leading journals such as the IEEE Transactions on Computers. Hadimioglu is a member of the IEEE, the ACM, and Sigma Xi. He has been an organizer of various workshops including, the ISCA Memory Wall (2000), ISCA Memory Performance Issues (2002, 2001) and HPCA8 Workshop on Network Processors (2002). He received Dedicated Faculty and Outstanding Faculty awards from Polytechnic students in 1995 and 1993, respectively. Peter Z. Onufryk received his B.S.E.E. from Rutgers University, M.S.E.E. from Purdue University, and Ph.D. in Electrical and Computer Engineering from Rutgers University. He is currently a director in the Internetworking Products Division at Integrated Device Technology, Inc. where he is responsible for architecture definition and validation of communications products. Before joining IDT, Peter was a researcher for thirteen years at AT&T Labs - Research (formally AT&T Bell Labs) where he worked on communications systems and parallel computer architectures. These included a number of parallel, cache-coherent multiprocessor and dataflow based machines that were targeted towards high performance military systems. Other work there focused on packet telephony and early network processors. Onufryk is a member of the IEEE. He was an organizer and program committee member of the HPCA8 Workshop on Network Processors 2002. Peter was the architect of four communications processors as well as numerous ASICs, boards, and systems.