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Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design 2015 ed. [Kõva köide]

  • Formaat: Hardback, 145 pages, kõrgus x laius: 235x155 mm, kaal: 424 g, 41 Illustrations, color; 10 Illustrations, black and white; XIX, 145 p. 51 illus., 41 illus. in color., 1 Hardback
  • Ilmumisaeg: 07-Aug-2014
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319087525
  • ISBN-13: 9783319087528
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  • Formaat: Hardback, 145 pages, kõrgus x laius: 235x155 mm, kaal: 424 g, 41 Illustrations, color; 10 Illustrations, black and white; XIX, 145 p. 51 illus., 41 illus. in color., 1 Hardback
  • Ilmumisaeg: 07-Aug-2014
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319087525
  • ISBN-13: 9783319087528
Teised raamatud teemal:

This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today’s multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays’ multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.

1 Introduction
1(28)
1.1 System-Level Design
3(7)
1.1.1 Levels of Abstraction
4(1)
1.1.2 The Y-Chart
5(1)
1.1.3 System-Level Design Methodologies
6(2)
1.1.4 Electronic System-Level Design Process
8(2)
1.2 Validation and Simulation
10(5)
1.2.1 Language Support for System-Level Design
10(2)
1.2.2 System Simulation Approaches
12(1)
1.2.3 Discrete Event Simulation
13(2)
1.3 Goals
15(1)
1.4 Overview
16(1)
1.5 Related Work
17(12)
1.5.1 The SpecC Language
17(5)
1.5.2 The SystemC Language
22(1)
1.5.3 The System-on-Chip Environment Design Flow
22(3)
1.5.4 Multicore Technology and Multithreaded Programming
25(2)
1.5.5 Efficient Model Validation and Simulation
27(2)
2 The ConcurrenC Model of Computation
29(10)
2.1 Motivation
29(1)
2.2 Models of Computation
30(2)
2.3 ConcurrenC MoC
32(3)
2.3.1 Relationship to C-based SLDLs
32(1)
2.3.2 ConcurrenC Features
33(1)
2.3.3 Communication Channel Library
34(1)
2.3.4 Relationship to KPN and SDF
35(1)
2.4 Case Study
35(4)
3 Synchronous Parallel Discrete Event Simulation
39(18)
3.1 Traditional Discrete Event Simulation
39(2)
3.2 SLDL Multithreading Semantics
41(2)
3.2.1 Cooperative Multithreading in SystemC
41(1)
3.2.2 Pre-emptive Multithreading in SpecC
42(1)
3.3 Synchronous Parallel Discrete Event Simulation
43(1)
3.4 Synchronization for Multicore Parallel Simulation
44(5)
3.4.1 Protecting Scheduling Resources
44(1)
3.4.2 Protecting Communication
45(1)
3.4.3 Channel Locking Scheme
45(2)
3.4.4 Automatic Code Instrumentation for Communication Protection
47(2)
3.5 Implementation Optimization for Multicore Simulation
49(1)
3.6 Experiments and Results
50(7)
3.6.1 Case Study on a H.264 Video Decoder
50(5)
3.6.2 Case Study on a JPEG Encoder
55(2)
4 Out-of-Order Parallel Discrete Event Simulation
57(18)
4.1 Motivation
57(2)
4.2 Out-of-Order Parallel Discrete Event Simulation
59(3)
4.2.1 Notations
59(3)
4.2.2 Out-of-Order PDES Scheduling Algorithm
62(1)
4.3 Out-of-Order PDES Conflict Analysis
62(9)
4.3.1 Thread Segments and Segment Graph
62(5)
4.3.2 Static Conflict Analysis
67(3)
4.3.3 Dynamic Conflict Detection
70(1)
4.4 Experimental Results
71(4)
4.4.1 An Abstract Model of a DVD Player
71(1)
4.4.2 A JPEG Encoder Model
72(1)
4.4.3 A Detailed H.264 Decoder Model
73(2)
5 Optimized Out-of-Order Parallel Discrete Event Simulation
75(20)
5.1 Optimized Compiler Using Instance Isolation
75(9)
5.1.1 Motivation
75(4)
5.1.2 Instance Isolation Without Code Duplication
79(1)
5.1.3 Definitions for the Optimized Static Conflict Analysis
80(1)
5.1.4 Algorithm for Static Conflict Analysis
81(2)
5.1.5 Experimental Results
83(1)
5.2 Optimized Scheduling Using Predictions
84(11)
5.2.1 State Prediction to Avoid False Conflicts
85(1)
5.2.2 Static Prediction Analysis
85(5)
5.2.3 Out-of-Order PDES Scheduling with Predictions
90(1)
5.2.4 Optimized Out-of-Order PDES Scheduling Conflict Checking with a Combined Prediction Table
91(1)
5.2.5 Experimental Results
91(4)
6 Comparison and Outlook
95(12)
6.1 Experimental Setup
95(5)
6.1.1 Experimental Environment Setup
95(1)
6.1.2 The Parallel Benchmark Models
96(2)
6.1.3 The Embedded Applications
98(2)
6.2 Parallel Discrete Event Simulation Overlook
100(7)
7 Utilizing the Parallel Simulation Infrastructure
107(24)
7.1 Introduction
107(3)
7.1.1 Creating Parallel System Models
108(1)
7.1.2 Shared Variables and Race Conditions
109(1)
7.2 Race Condition Detection for ESL Models
110(1)
7.3 Dynamic Segment Aware Detection
111(9)
7.3.1 Automatic Race Condition Diagnosis
112(1)
7.3.2 Race Condition Elimination Infrastructure
113(3)
7.3.3 Experiments and Results
116(1)
7.3.4 Case Study: A Parallel H.264 Video Decoder
116(1)
7.3.5 Case Study: A Parallel H.264 Video Encoder
117(2)
7.3.6 Additional Embedded Applications
119(1)
7.3.7 Conclusions for Dynamic Segment Aware Detection
120(1)
7.4 Static Segment Aware Detection
120(11)
7.4.1 Segment Graph Data Structures
120(2)
7.4.2 Determining MHP Segments
122(3)
7.4.3 MHP Algorithm for Race Condition Analysis
125(2)
7.4.4 Experiments and Results
127(2)
7.4.5 Conclusions for Static Segment Aware Detection
129(2)
8 Conclusions
131(6)
8.1 Contributions
131(3)
8.1.1 A Model of Computation for System-Level Design
132(1)
8.1.2 A Synchronous Parallel Discrete Event Simulator
132(1)
8.1.3 An Advanced Parallel Discrete Event Simulation Approach
133(1)
8.1.4 An Infrastructure for Increasing Modeling Observability
133(1)
8.2 Future Work
134(1)
8.2.1 Model Parallelization
134(1)
8.2.2 Multithreading Library Support
134(1)
8.2.3 Extension to the SystemC SLDL
134(1)
8.2.4 Parallel Full System Validation
135(1)
8.3 Concluding Remarks
135(2)
References 137(6)
Index 143