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1 | (28) |
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3 | (7) |
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1.1.1 Levels of Abstraction |
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4 | (1) |
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5 | (1) |
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1.1.3 System-Level Design Methodologies |
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6 | (2) |
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1.1.4 Electronic System-Level Design Process |
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8 | (2) |
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1.2 Validation and Simulation |
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10 | (5) |
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1.2.1 Language Support for System-Level Design |
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10 | (2) |
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1.2.2 System Simulation Approaches |
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12 | (1) |
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1.2.3 Discrete Event Simulation |
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13 | (2) |
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15 | (1) |
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16 | (1) |
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17 | (12) |
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17 | (5) |
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1.5.2 The SystemC Language |
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22 | (1) |
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1.5.3 The System-on-Chip Environment Design Flow |
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22 | (3) |
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1.5.4 Multicore Technology and Multithreaded Programming |
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25 | (2) |
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1.5.5 Efficient Model Validation and Simulation |
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27 | (2) |
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2 The ConcurrenC Model of Computation |
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29 | (10) |
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29 | (1) |
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2.2 Models of Computation |
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30 | (2) |
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32 | (3) |
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2.3.1 Relationship to C-based SLDLs |
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32 | (1) |
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2.3.2 ConcurrenC Features |
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33 | (1) |
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2.3.3 Communication Channel Library |
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34 | (1) |
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2.3.4 Relationship to KPN and SDF |
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35 | (1) |
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35 | (4) |
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3 Synchronous Parallel Discrete Event Simulation |
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39 | (18) |
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3.1 Traditional Discrete Event Simulation |
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39 | (2) |
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3.2 SLDL Multithreading Semantics |
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41 | (2) |
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3.2.1 Cooperative Multithreading in SystemC |
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41 | (1) |
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3.2.2 Pre-emptive Multithreading in SpecC |
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42 | (1) |
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3.3 Synchronous Parallel Discrete Event Simulation |
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43 | (1) |
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3.4 Synchronization for Multicore Parallel Simulation |
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44 | (5) |
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3.4.1 Protecting Scheduling Resources |
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44 | (1) |
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3.4.2 Protecting Communication |
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45 | (1) |
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3.4.3 Channel Locking Scheme |
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45 | (2) |
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3.4.4 Automatic Code Instrumentation for Communication Protection |
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47 | (2) |
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3.5 Implementation Optimization for Multicore Simulation |
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49 | (1) |
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3.6 Experiments and Results |
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50 | (7) |
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3.6.1 Case Study on a H.264 Video Decoder |
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50 | (5) |
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3.6.2 Case Study on a JPEG Encoder |
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55 | (2) |
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4 Out-of-Order Parallel Discrete Event Simulation |
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57 | (18) |
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57 | (2) |
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4.2 Out-of-Order Parallel Discrete Event Simulation |
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59 | (3) |
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59 | (3) |
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4.2.2 Out-of-Order PDES Scheduling Algorithm |
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62 | (1) |
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4.3 Out-of-Order PDES Conflict Analysis |
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62 | (9) |
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4.3.1 Thread Segments and Segment Graph |
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62 | (5) |
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4.3.2 Static Conflict Analysis |
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67 | (3) |
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4.3.3 Dynamic Conflict Detection |
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70 | (1) |
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71 | (4) |
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4.4.1 An Abstract Model of a DVD Player |
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71 | (1) |
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4.4.2 A JPEG Encoder Model |
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72 | (1) |
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4.4.3 A Detailed H.264 Decoder Model |
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73 | (2) |
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5 Optimized Out-of-Order Parallel Discrete Event Simulation |
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75 | (20) |
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5.1 Optimized Compiler Using Instance Isolation |
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75 | (9) |
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75 | (4) |
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5.1.2 Instance Isolation Without Code Duplication |
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79 | (1) |
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5.1.3 Definitions for the Optimized Static Conflict Analysis |
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80 | (1) |
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5.1.4 Algorithm for Static Conflict Analysis |
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81 | (2) |
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5.1.5 Experimental Results |
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83 | (1) |
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5.2 Optimized Scheduling Using Predictions |
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84 | (11) |
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5.2.1 State Prediction to Avoid False Conflicts |
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85 | (1) |
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5.2.2 Static Prediction Analysis |
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85 | (5) |
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5.2.3 Out-of-Order PDES Scheduling with Predictions |
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90 | (1) |
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5.2.4 Optimized Out-of-Order PDES Scheduling Conflict Checking with a Combined Prediction Table |
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91 | (1) |
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5.2.5 Experimental Results |
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91 | (4) |
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95 | (12) |
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95 | (5) |
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6.1.1 Experimental Environment Setup |
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95 | (1) |
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6.1.2 The Parallel Benchmark Models |
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96 | (2) |
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6.1.3 The Embedded Applications |
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98 | (2) |
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6.2 Parallel Discrete Event Simulation Overlook |
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100 | (7) |
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7 Utilizing the Parallel Simulation Infrastructure |
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107 | (24) |
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107 | (3) |
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7.1.1 Creating Parallel System Models |
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108 | (1) |
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7.1.2 Shared Variables and Race Conditions |
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109 | (1) |
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7.2 Race Condition Detection for ESL Models |
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110 | (1) |
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7.3 Dynamic Segment Aware Detection |
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111 | (9) |
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7.3.1 Automatic Race Condition Diagnosis |
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112 | (1) |
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7.3.2 Race Condition Elimination Infrastructure |
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113 | (3) |
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7.3.3 Experiments and Results |
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116 | (1) |
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7.3.4 Case Study: A Parallel H.264 Video Decoder |
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116 | (1) |
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7.3.5 Case Study: A Parallel H.264 Video Encoder |
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117 | (2) |
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7.3.6 Additional Embedded Applications |
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119 | (1) |
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7.3.7 Conclusions for Dynamic Segment Aware Detection |
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120 | (1) |
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7.4 Static Segment Aware Detection |
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120 | (11) |
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7.4.1 Segment Graph Data Structures |
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120 | (2) |
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7.4.2 Determining MHP Segments |
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122 | (3) |
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7.4.3 MHP Algorithm for Race Condition Analysis |
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125 | (2) |
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7.4.4 Experiments and Results |
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127 | (2) |
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7.4.5 Conclusions for Static Segment Aware Detection |
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129 | (2) |
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131 | (6) |
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131 | (3) |
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8.1.1 A Model of Computation for System-Level Design |
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132 | (1) |
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8.1.2 A Synchronous Parallel Discrete Event Simulator |
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132 | (1) |
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8.1.3 An Advanced Parallel Discrete Event Simulation Approach |
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133 | (1) |
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8.1.4 An Infrastructure for Increasing Modeling Observability |
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133 | (1) |
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134 | (1) |
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8.2.1 Model Parallelization |
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134 | (1) |
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8.2.2 Multithreading Library Support |
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134 | (1) |
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8.2.3 Extension to the SystemC SLDL |
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134 | (1) |
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8.2.4 Parallel Full System Validation |
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135 | (1) |
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135 | (2) |
References |
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137 | (6) |
Index |
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143 | |