Muutke küpsiste eelistusi

Oversampled Delta-Sigma Modulators: Analysis, Applications and Novel Topologies 2003 ed. [Kõva köide]

  • Formaat: Hardback, 226 pages, kõrgus x laius: 240x160 mm, kaal: 580 g, 47 Illustrations, black and white; XII, 226 p. 47 illus., 1 Hardback
  • Ilmumisaeg: 31-Jul-2003
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1402074204
  • ISBN-13: 9781402074202
Teised raamatud teemal:
  • Kõva köide
  • Hind: 76,49 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Tavahind: 89,99 €
  • Säästad 15%
  • Raamatu kohalejõudmiseks kirjastusest kulub orienteeruvalt 2-4 nädalat
  • Kogus:
  • Lisa ostukorvi
  • Tasuta tarne
  • Tellimisaeg 2-4 nädalat
  • Lisa soovinimekirja
  • Formaat: Hardback, 226 pages, kõrgus x laius: 240x160 mm, kaal: 580 g, 47 Illustrations, black and white; XII, 226 p. 47 illus., 1 Hardback
  • Ilmumisaeg: 31-Jul-2003
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1402074204
  • ISBN-13: 9781402074202
Teised raamatud teemal:
Kozak (U. of Rochester) and Kale (U. of Westminster, UK) present theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Throughout, the authors make abundant use of mathematical equations to analyze both single-and multi-stage architectures. Proof that appropriately set initial conditions generate tone-free output (provided that the modulator order is at least three) is examined. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. The volume also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators, generalized for any interleaving number and modulator order. Of likely interest to graduate students, researchers, and practicing circuit designers in the areas of delta-sigma based data converters and Fractional-N PLL frequency synthesizer design. Lacks a subject index. Annotation (c) Book News, Inc., Portland, OR (booknews.com)

The analysis of the quantization noise in delta-sigma modulators is not a trivial task. State-of-the-art analysis methods include modelling the quantization noise as a uniform distributed white noise. However, it is not uncommon to observe limit cycle oscillations and tones at the output of a delta-sigma modulator. In most of the applications, these limit cycles and tones are strictly objectionable. Such an application, for instance, is a Fractional-N PLL frequency synthesizer, where idle tones and limit cycles generated from the delta-sigma modulator directly appear in the synthesized RF waveform as spurious components. The relatively small conversion bandwidth is another important limitation of delta-sigma modulators. Due to their oversampling nature, delta-sigma modulators have been used in low frequency applications. Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies presents theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Extensive mathematical equations are included throughout the book to analyze both single-stage and multi-stage architectures. It has been proved that appropriately set initial conditions generate tone free output, provided that the modulator order is at least three. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. Furthermore, the book also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators. The topologies have been generalized for any interleaving number and modulator order. Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies is full of design and analysis techniques. The book contains sufficient detail that enables readers with little background in the subject to easily follow the material in it. Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies will be of interest to graduate students, researchers, and practising circuit designers in the areas of delta-sigma based data converters and Fractional-N PLL frequency synthesizer design.

Arvustused

From the reviews:



"This book describes the principles of operation of oversampled (delta sigma symbol) modulators and gives an exact analysis and speed limitations of these non-linear complex circuits. The book should be useful both as a reference book to graduate students, and researchers and practising engineers in the field of mixed-signal VLSI design. After finishing the text, the total picture of design including analysis, modeling, simulation, and implementation of this type of circuits is presented to the reader. I highly recommend this book." (Mile Stojcev, Microelectronics Reliability, Vol. 44, 2004)

Preface xi
Introduction
1(6)
Aims and Motivations
1(3)
Original Contributions
4(1)
Outline of the Research Monograph
5(2)
Basic Principles of Delta-Sigma Modulation
7(24)
Nyquist Rate Converters
8(2)
Quantization Noise
10(3)
Oversampling Advantage
13(2)
ΔΣ Modulation
15(6)
Limit Cycle Oscillations and Tones
21(2)
Dithering
21(2)
Chaotic ΔΣ Modulators
23(1)
Higher-order ΔΣ Modulators
23(4)
Single-stage Architectures
24(1)
Multi-stage Architectures
25(2)
Multi-bit ΔΣ Converters
27(1)
State-of-the-art Analysis
28(3)
Analysis of Mash Delta-Sigma Modulators with DC Inputs
31(48)
Introduction
32(3)
Non-linear Difference Equations
35(8)
First-order ΔΣ Modulator
35(5)
Higher-order MASH ΔΣ Modulator
40(3)
Statistics of the Quantizer Error Sequence
43(19)
Preliminaries
43(2)
First-order ΔΣ Modulator
45(7)
Higher-order MASH ΔΣ Modulator
52(10)
Simulation Results
62(8)
Output Spectrum
70(1)
Digital Realization of Irrational Initial Condition
71(3)
Conclusion
74(5)
Analysis of Single-Stage Delta-Sigma Modulators with DC Inputs
79(40)
Motivation behind the Work
79(1)
Uniform Quantizer in the No-Overload Region
80(3)
Non-linear Difference Equations
83(12)
Second-order ΔΣ Modulator
83(3)
Higher-order ΔΣ Modulator
86(9)
No-Overload Stability Criterion
95(4)
Solution to the Non-linear Difference Equation
99(7)
Statistics of the Quantizer Error Sequence
106(3)
Second-order ΔΣ Modulator
107(1)
Higher-order ΔΣ Modulator
108(1)
Fundamental Result
109(1)
Simulation Results
109(3)
Output Spectrum
112(4)
Error-Feedback Topology
116(2)
Conclusion
118(1)
Fractional-N PLL Frequency Synthesizers
119(48)
Introduction
120(1)
Analysis of PLLs
121(10)
Small-signal Model
122(2)
Second-order Systems
124(4)
Charge-pump PLL
128(3)
The Fractional-N Concept
131(7)
First Generation Fractional-N PLL Synthesizers
132(2)
Higher-order ΔΣ Modulation for Modulus Control
134(4)
Design and Simulation of Fractional-N PLL Frequency Synthesizers
138(19)
Linear Model of the Charge-Pump PLL
138(3)
Design Issues
141(4)
Computer Simulation Model
145(7)
Overall Fractional-N PLL Simulation Results
152(5)
Pipelined Implementation of Mash ΔΣ Modulators
157(8)
Conclusion
165(2)
Time-Interleaved Delta-Sigma Modulators
167(54)
Introduction
168(2)
Block Digital Filtering Approach
170(5)
Time-Interleaved ΔΣ Modulators with Reduced Complexity
175(7)
Simulations
182(2)
Implementation Issues
184(8)
Finite Op-amp Gain
184(1)
Op-amp dc Offset
185(2)
Mismatch Effects
187(3)
Sampling Clock Jitter
190(1)
Critical Delay Problem
190(2)
Hardware Comparison
192(2)
Higher-order Time-Interleaved ΔΣ Modulators
194(12)
Cascaded Integrators with Feed-Forward Summation Topology
195(4)
Cascaded Integrators with Distributed Feedback as well as Feed-forward Branch Topology
199(2)
Simulations
201(2)
Coefficient Mismatches
203(3)
Zero-Insertion Interpolation Time-Interleaving
206(9)
Further Practical Issues
215(3)
Sampling Clock Jitter Effects
215(2)
Branch Mismatch Effects
217(1)
Conclusion
218(3)
References 221