In his introduction to Very-high-level Hardware Description Language (VHDL), Reidenbach has in mind electrical or computer engineering students in their second or third year, but says the treatment could also be useful to any engineer exploring the use of VHDL as a digital design vehicle. He assumes readers to have prior experience-either academically or professionally-in software programming using a language such as C, and in Boolean logic design. His topics include the VHDL design environment, modeling case studies, test bench development, specialized code examples, and design reuse. Annotation ©2022 Ringgold, Inc., Portland, OR (protoview.com)
The VHSIC Hardware Description Language (VHDL) is one of the two most popular languages used to design digital logic circuits. This book provides a comprehensive introduction to the syntax and the most commonly used features of VHDL. It also presents a formal digital design process and the best-case design practices that have been developed over more than twenty-five years of VHDL design experience by the author in military ground and satellite communication systems. Unlike other books on this subject, this real-world professional experience captures not only the what of VHDL, but also the how. Throughout the book, recommended methods for performing digital design are presented along with the common pitfalls and the techniques used to successfully avoid them. Written for students learning VHDL for the first time as well as professional development material for experienced engineers, this book’s contents minimize design time while maximizing the probability of first-time design success.
