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Practical Guide to Verilog-A: Mastering the Modeling Language for Analog Devices, Circuits, and Systems 1st ed. [Pehme köide]

  • Formaat: Paperback / softback, 319 pages, kõrgus x laius: 235x155 mm, kaal: 545 g, 26 Illustrations, black and white; XXXV, 319 p. 26 illus., 1 Paperback / softback
  • Ilmumisaeg: 15-Sep-2022
  • Kirjastus: APress
  • ISBN-10: 1484263502
  • ISBN-13: 9781484263501
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Practical Guide to Verilog-A: Mastering the Modeling Language for Analog Devices, Circuits, and Systems 1st ed.Suurem pilt
  • Formaat: Paperback / softback, 319 pages, kõrgus x laius: 235x155 mm, kaal: 545 g, 26 Illustrations, black and white; XXXV, 319 p. 26 illus., 1 Paperback / softback
  • Ilmumisaeg: 15-Sep-2022
  • Kirjastus: APress
  • ISBN-10: 1484263502
  • ISBN-13: 9781484263501
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781484263501.html
Märksõnad:
Discover how Verilog-A is particularly designed to describe behavior and connectivity of circuits and system components for analog SPICE-class simulators, or for continuous time (SPICE-based) kernels in Verilog-AMS simulators. With continuous updates since it’s release 30 years ago, this practical guide provides a comprehensive foundation and understanding to the  modeling language in its most recent standard formulation. 

With the introduction of language extensions to support compact device modeling, the Verilog-A has become today de facto standard language in the electronics industry for coding compact models of active and passive semiconductor devices. You'll gain an in depth look at how analog circuit simulators work, solving system equations, modeling of components from other physical domains, and modeling the same physical circuits and systems at various levels of detail and at different levels of abstraction.

All industry standard compact models released by Si2 Compact Model Coalition (CMC) as well as compact models of emerging nano-electronics devices released by New Era Electronic Devices and Systems (NEEDS) initiative are coded in Verilog-A. This book prepares you for the current trends in the neuromorphic computing, hardware customization for artificial intelligence applications as well as circuit design for internet of things (IOT) will only increase the need for analog simulation modeling and make Verilog-A even more important as a multi-domain component-oriented modeling language.

Let A Practical Guide to Verilog-A be the initial step in learning the extended mixed-signal Verilog-AMS hardware description language.

What You'll Learn
  • Review the hardware description and modeling language Verilog-A in its most recent standard formulation.
  • Code new compact models of active and passive semiconductor devices as well as new models for emerging circuit components from different physical disciplines.
  • Extend the application of SPICE-like circuit simulators to non-electronics field (neuromorphic, thermal, mechanical, etc systems).
  • Apply the initial steps towards the extended mixed-signal Verilog-AMS hardware description language.
Who This Book Is For
Electronic circuit designers and SPICE simulation model developers in academia and industry. Developers of electronic design automation (EDA) tools. Engineers, scientists and students of various disciplines using SPICE-like simulators for research and development.

About the Author xv
About the Technical Reviewer xvii
Acknowledgments xix
Introduction xxi
Chapter 1 Lexical Basis
1(16)
Character Set and Tokens
1(2)
Comments
3(1)
Identifiers
4(1)
Simple Identifiers
4(1)
Escaped Identifiers
5(1)
Hierarchical Names
6(1)
Reserved Words
6(1)
System Names
7(1)
Compiler Directives
7(1)
Numerical Literals
8(1)
Integer Literals
8(3)
Real Literals
11(2)
String Literals
13(1)
Operators
14(1)
Punctuators
15(2)
Chapter 2 Basic Types and Expressions
17(16)
Basic Types
17(1)
Integer Types
17(1)
Real Types
18(1)
String Types
19(1)
Expressions
20(1)
Primary Expressions
20(2)
Arithmetic Expressions
22(1)
Relational Expressions
23(1)
Logical Expressions
24(1)
Bitwise Expressions
25(1)
Conditional Expressions
26(1)
Concatenated Expressions
26(2)
Expression Evaluation Order
28(1)
Operator Precedence
28(1)
Parenthesized Expressions
29(1)
Short-Circuit Evaluation
30(1)
Expression Containers
30(1)
Assignment Patterns
30(1)
Ranges
31(2)
Chapter 3 Net-Discipline Types
33(20)
Defining Signal Natures
33(1)
Base Natures
34(3)
Derived Natures
37(1)
Predefined Natures
38(3)
Defining Net-Discipline Types
41(1)
Nature Binding Statements
41(2)
Domain Binding Statements
43(1)
Nature Override Statements
43(1)
Deriving Natures from Disciplines
44(1)
Discipline Compatibility
44(2)
Predefined Disciplines
46(1)
Net Declarations
47(1)
Scalar Nets
47(1)
Vector Nets
48(1)
Ground Nets
49(1)
Net Initialization
50(1)
Accessing Net Attributes
51(2)
Chapter 4 Modules and Ports
53(16)
Defining Module Connectivity
53(1)
Declaring Port Directions
54(3)
Declaring Port Types
57(3)
Connecting Modules by Instantiation
60(1)
Explicit Port Mapping
61(2)
Positional Port Mapping
63(1)
Top-Level Instantiation and $root
64(2)
Implicit Nets
66(1)
Instantiation of SPICE Primitives
67(2)
Chapter 5 Parameters
69(16)
Parameter Declarations
69(1)
Simple Parameters
70(1)
Array Parameters
71(1)
Permissible Value Ranges
72(3)
Parameter Aliases
75(1)
Local Parameters
76(1)
Overriding Parameters
76(1)
Instance Parameter Override
76(4)
Hierarchical Parameter Override
80(1)
Hierarchical System Parameters
81(4)
Chapter 6 Paramsets
85(12)
Introducing Paramsets
85(3)
Defining Paramsets
88(1)
Paramset Parameters
88(2)
Parameter Override Statements
90(2)
Other Paramset Statements
92(1)
Paramset Instantiation
92(5)
Chapter 7 Procedural Programming
97(18)
Variables
97(1)
Simple Variables
98(1)
Array Variables
99(1)
Procedural Blocks
100(1)
Analog Blocks
100(1)
Block Procedural Statements
101(2)
Assignment Statements
103(1)
Scalar Assignments
104(1)
Array Assignments
105(1)
Conditional Statements
106(1)
If Statement
106(2)
Case Statement
108(1)
Looping Statements
109(1)
While Statement
110(1)
For Statement
111(1)
Repeat Statement
112(3)
Chapter 8 Branches
115(20)
Declaring Branches
115(1)
Scalar Branches
115(2)
Vector Branches
117(2)
Port Branches
119(1)
Branch Signals
120(1)
Signal Directions
120(1)
Signal Access Functions
121(2)
Unnamed Branches
123(2)
Contributing Branch Signals
125(1)
Direct Contribution Statements
125(2)
Indirect Contribution Statements
127(2)
Probe Branches
129(1)
Value Retention
130(2)
Switch Branches
132(3)
Chapter 9 Derivative and Integral Operators
135(18)
Time Derivative Operator
135(1)
Case Study: DC Motor
136(2)
Time Integrator Operator
138(1)
Case Study: Chemical Reaction System
139(3)
Circular Integrator Operator
142(2)
Case Study: Voltage-Controlled Oscillator
144(1)
Indirect Contribution Equations
145(2)
Case Study: Accelerometer
147(2)
Probe Derivative Operator
149(4)
Chapter 10 Built-in Math Functions
153(12)
Deterministic Functions
153(1)
Logarithmic and Power Functions
154(1)
Trigonometric Functions
155(1)
Hyperbolic Functions
156(1)
Limiting and Rounding Functions
157(1)
Probabilistic Functions
158(1)
Random Number Generation Function
158(2)
Statistical Distribution Functions
160(5)
Chapter 11 User-Defined Functions
165(10)
Defining Functions
165(1)
Formal Arguments
166(1)
A Return Variable
167(1)
A Procedural Statement
168(2)
Calling Functions
170(1)
Function References
170(2)
Using Functions in Expressions
172(1)
Function Called As Statements
172(3)
Chapter 12 Lookup Tables
175(14)
Table Data Structure
175(1)
Jagged Array Grids
176(2)
Preparing Table Data
178(2)
Lookup Table Function
180(1)
Input Variables and Data Source
181(2)
Control String
183(6)
Chapter 13 Small-Signal Functions
189(12)
AC Analysis
190(1)
AC Stimulus Function
190(2)
Noise Analysis
192(1)
White Noise Function
193(1)
Flicker Noise Function
194(1)
Look-Up Table Noise Functions
195(4)
Correlated Noise Sources
199(2)
Chapter 14 Filters
201(14)
Time-Domain Filters
201(1)
Absolute Delay Filter
201(1)
Transition Filter
202(2)
Slew Filter
204(1)
Frequency-Domain Filters
205(1)
Laplace Transform Filters
206(4)
The Z-Transform Filters
210(5)
Chapter 15 Events
215(14)
Event Control Statements
215(2)
Global Event Functions
217(2)
Monitored Event Functions
219(1)
Cross Function
220(4)
Above Function
224(2)
Timer Function
226(3)
Chapter 16 Runtime Support
229(20)
Elaboration Queries
229(1)
Port Connections
229(1)
Parameter Overrides
230(1)
Simulation Queries
231(1)
Analysis Type
231(2)
Kernel Parameters
233(3)
Dynamic Probing
236(2)
Solver Support
238(1)
Announcing Discontinuity
238(3)
Bounding Time Step
241(1)
Limiting Iteration Steps
242(4)
Simulation Control
246(1)
Announcing Severity
246(1)
Terminating Simulation
247(2)
Chapter 17 Input and Output
249(18)
File Management
249(1)
Opening Files
249(3)
File Positioning
252(2)
Error Status
254(1)
Detecting End-of-File
254(1)
Flushing Output
255(1)
Closing Files
255(1)
Reading Data
255(1)
Reading a Line from a File
255(1)
Reading Formatted Data
256(3)
Displaying and Writing Data
259(1)
Text Output
259(1)
File Output
260(2)
Writing Data to a String
262(1)
Escape Sequences
263(4)
Chapter 18 Generative Programming
267(14)
Generate Blocks
267(2)
Generate Statements
269(1)
Generate Regions
269(1)
Conditional Generation
269(3)
Looping Generation
272(4)
Hierarchy Scope and Names
276(2)
Order of Elaboration
278(3)
Chapter 19 Attributes
281(12)
Introducing Attributes
281(1)
Attribute Assignments
281(2)
Attribute Instances
283(3)
Standard Attributes
286(1)
Simulation Reports
286(2)
Output Variables
288(2)
Port Discipline Override
290(3)
Chapter 20 Compiler Directives
293(10)
File Inclusion
293(2)
Macro Definition
295(1)
Object-like Macros
295(1)
Function-like Macros
296(2)
Undefining Macros
298(1)
Predefined Macros
299(1)
Conditional Compilation
299(3)
Default Transition Directive
302(1)
Appendix 303(1)
Reserved Words in Verilog-A 303(1)
Keywords 303(1)
Other Reserved Words 304(2)
SPICE Compatibility 306(3)
Index 309
Dr. Slobodan Mijalkovic is a Senior R&D Engineer at Silvaco, Inc., specialized in semiconductor device and integrated circuit modeling for electronic design automation (EDA) software tools. Before joining Silvaco Europe, he was a Principal Researcher in HiTeC Laboratory at Delft University of Technology in the Netherlands, where he led a team for standardization of the Mextram bipolar transistor model with Compact Model Coalition (CMC). Formerly, he was an Assistant and an Associate Professor with the Department of Microelectronics at Faculty of Electronics Engineering, University of Nis in Serbia (Yugoslavia). Dr. Mijalkovic has authored 50 cited publications including the monograph Multigrid Methods for Process Simulation published by Springer. In the period 2002-2006 he has set and chaired four editions of Compact Modeling for RF Application (CMRF) workshops that strongly contributed to the acceptance of Verilog-A as a standard compact modeling language. He is a senior Member of IEEE and currently a member of the IEEE EDS Compact Modeling Committee.