Muutke küpsiste eelistusi

Principles of Verilog Digital Design [Kõva köide]

  • Formaat: Hardback, 590 pages, kõrgus x laius: 234x156 mm, kaal: 879 g, 56 Tables, black and white; 364 Line drawings, black and white; 5 Halftones, black and white; 369 Illustrations, black and white
  • Ilmumisaeg: 08-Mar-2022
  • Kirjastus: CRC Press
  • ISBN-10: 1032034122
  • ISBN-13: 9781032034126
Teised raamatud teemal:
Principles of Verilog Digital DesignSuurem pilt
  • Formaat: Hardback, 590 pages, kõrgus x laius: 234x156 mm, kaal: 879 g, 56 Tables, black and white; 364 Line drawings, black and white; 5 Halftones, black and white; 369 Illustrations, black and white
  • Ilmumisaeg: 08-Mar-2022
  • Kirjastus: CRC Press
  • ISBN-10: 1032034122
  • ISBN-13: 9781032034126
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781032034126.html
Märksõnad:
Covering both the fundamentals and the in-depth topics related to Verilog digital design, both students and experts can benefit from reading this book by gaining a comprehensive understanding of how modern electronic products are designed and implemented. Principles of Verilog Digital Design contains many hands-on examples accompanied by RTL codes that together can bring a beginner into the digital design realm without needing too much background in the subject area.

This book has a particular focus on how to transform design concepts into physical implementations using architecture and timing diagrams. Common mistakes a beginner or even an experienced engineer can make are summarized and addressed as well. Beyond the legal details of Verilog codes, the book additionally presents what uses Verilog codes have through some pertinent design principles.

Moreover, students reading this book will gain knowledge about system-level design concepts. Several ASIC designs are illustrated in detail as well. In addition to design principles and skills, modern design methodology and how it is carried out in practice today are explored in depth as well.
Preface xiii
Acknowledgments xv
Chapter 1 Introduction
1(28)
1.1 Integrated Circuit Industry
1(1)
1.2 Digital Era
2(3)
1.2.1 AID and D/A Conversion
2(1)
1.2.2 Digital Systems and Digital Logic
3(2)
1.3 Boolean Algebra and Logic Design
5(2)
1.4 Computer-Aided Design
7(1)
1.5 ASIC Design Flow
8(4)
1.6 Hardware Description Language
12(2)
1.7 Design Entry Based on Register-Transfer Level
14(4)
1.8 Functional Verification
18(3)
1.9 Logic Synthesis
21(1)
1.10 Timing Verification
22(3)
1.10.1 Dynamic Timing Analysis
22(1)
1.10.2 Static Timing Analysis
23(2)
1.11 Physical Design
25(1)
1.11.1 Design Implementation
25(1)
1.12 More on Design Flow
26(1)
1.13 Further Reading
27(2)
Problems
28(1)
Chapter 2 Fundamentals of Verilog
29(46)
2.1 Introduction to Verilog HDL
29(1)
2.2 Module and Port
30(7)
2.3 Number Representation of Verilog
37(2)
2.4 Data Type
39(4)
2.4.1 Nets
39(1)
2.4.2 Registers
40(2)
2.4.3 Parameters
42(1)
2.4.4 Choosing Data Types for Ports
42(1)
2.5 Continuous Assignment
43(1)
2.6 Procedural Construct
44(8)
2.6.1 Initial Block
44(3)
2.6.2 Always Block
47(4)
2.6.3 Named Block of Procedural Construct
51(1)
2.7 Verilog Primitives
52(2)
2.8 Expression
54(12)
2.8.1 2's Complement Number
54(2)
2.8.2 Operand
56(2)
2.8.3 Operators
58(1)
2.8.3.1 Arithmetic Operators
59(2)
2.8.3.2 Sign Operators
61(1)
2.8.3.3 Relational Operators
61(1)
2.8.3.4 Equality and Inequality Operators
61(1)
2.8.3.5 Logical Comparison Operators
62(1)
2.8.3.6 Logical Bit-Wise Operators
63(1)
2.8.3.7 Shift Operators
63(1)
2.8.3.8 Concatenation and Replication Operators
64(1)
2.8.3.9 Reduction Operators
65(1)
2.8.3.10 Conditional Operator
65(1)
2.9 Simulation Environment
66(4)
2.10 Further Reading
70(5)
Problems
71(4)
Chapter 3 Advanced Verilog Topics
75(54)
3.1 Abstract Levels
75(1)
3.2 If-Else Statement
75(5)
3.3 Case, Casez, and Casex Statements
80(4)
3.4 For Loop Statement
84(3)
3.5 Function and Task
87(3)
3.6 Parameterized Design
90(1)
3.7 Delay in Circuits
91(11)
3.7.1 Load Reduction by Buffer
93(1)
3.7.2 Delay Modeling
94(4)
3.7.2.1 Delay Characterization
98(2)
3.7.3 Delay Control
100(2)
3.7.4 Path Delay
102(1)
3.8 Blocking and Non-Blocking Assignments
102(8)
3.9 Some Useful System Tasks
110(3)
3.9.1 Simulation
110(1)
3.9.2 I/O
110(1)
3.9.3 Timing Check
110(3)
3.9.4 Data Conversion
113(1)
3.10 Advanced Verilog Simulation
113(3)
3.10.1 Compiler Directive
113(2)
3.10.2 Timing Simulation
115(1)
3.11 Advanced Verilog Features
116(1)
3.11.1 ANSIC-C Style Port Declaration
116(1)
3.11.2 Generate Statement
116(1)
3.12 Further Reading
117(12)
Problems
118(11)
Chapter 4 Number Representation
129(20)
4.1 Precision and Resolution of a Number Representation
129(1)
4.2 Fixed-Point Numbers
130(14)
4.2.1 Representation
130(1)
4.2.1.1 Binary to Decimal Number Conversion
130(5)
4.2.1.2 Decimal to Binary Number Conversion
135(2)
4.2.1.3 Digital Signal Processing Applications
137(2)
4.2.2 Operations
139(1)
4.2.2.1 Addition Operation
139(1)
4.2.2.2 Multiplication Operation
140(1)
4.2.2.3 Signal Processing
141(3)
4.3 Floating-Point Numbers
144(1)
4.4 Other Binary Numbers
145(1)
4.5 Further Reading
146(3)
Problems
147(2)
Chapter 5 Combinational Circuits
149(60)
5.1 Dataflow Description
149(3)
5.2 Behavioral Description
152(6)
5.3 Structural Description
158(1)
5.4 Combinational Loop
158(2)
5.5 Basic Building Blocks of Combinational Circuits: Logic Units
160(14)
5.5.1 Multiplexer
160(1)
5.5.2 Demultiplexer
161(1)
5.5.3 Comparator
162(1)
5.5.4 Shifter and Rotator
163(1)
5.5.5 Encoder
164(3)
5.5.6 Priority Encoder
167(1)
5.5.7 Decoder
168(4)
5.5.8 Bubble Sorting
172(2)
5.6 Basic Building Blocks of Combinational Circuits: Arithmetic Units
174(28)
5.6.1 Half Adder
174(2)
5.6.2 Full Adder
176(3)
5.6.3 Signed Arithmetic
179(2)
5.6.3.1 Fundamentals of Addition and Subtraction Using 2's Complement
181(2)
5.6.3.2 Addition and Subtraction in 2's Complement Using Verilog
183(3)
5.6.3.3 Multiplication in 2's Complement Using Verilog
186(1)
5.6.3.4 Bit Width Design
187(1)
5.6.3.5 More on Overflow Detection
188(6)
5.6.3.6 Bit Width Design of Digital Signal Processing System
194(1)
5.6.4 Arithmetic Logic Unit
195(1)
5.6.5 Carry Look-Ahead Adder
196(1)
5.6.6 Complex Multiplier
197(4)
5.6.7 More on Sizing and Signing
201(1)
5.7 Further Reading
202(7)
Problems
204(5)
Chapter 6 Sequential Circuits
209(46)
6.1 Introduction to Sequential Circuits
209(12)
6.1.1 Latch
210(4)
6.1.2 Flip-Hop
214(3)
6.1.3 Setup and Hold Times of Flip-Flops
217(3)
6.1.4 Master-Slave Flip-Flop
220(1)
6.1.5 Latch vs. Flip-Flop
221(1)
6.2 Behavioral Description
221(4)
6.3 Structural Description
225(1)
6.4 Basic Building Blocks of Sequential Circuits
225(21)
6.4.1 Registers
225(1)
6.4.2 Shift Registers
226(2)
6.4.3 Register Files
228(2)
6.4.4 State Machine
230(1)
6.4.4.1 State Reduction
230(1)
6.4.4.2 State Assignment
231(2)
6.4.5 Counter
233(1)
6.4.5.1 Synchronous Counter
233(2)
6.4.5.2 Asynchronous Counter
235(4)
6.4.6 FIFO
239(4)
6.4.7 Problems When Interacting with Signals from Different Procedural Blocks
243(3)
6.5 Further Reading
246(9)
Problems
247(8)
Chapter 7 Digital System Designs
255(106)
7.1 System-Level Design: Moving from the Virtual to the Real
255(30)
7.1.1 Pipelined Design
259(4)
7.1.2 FIFO for Buffering Data
263(2)
7.1.3 Arbiter
265(2)
7.1.4 Interconnect
267(1)
7.1.4.1 Buses
268(10)
7.1.4.2 Crossbar Switches
278(6)
7.1.4.3 Interconnect Networks
284(1)
7.2 System-Level Design: Memory System
285(21)
7.2.1 Static Random-Access Memory
286(10)
7.2.1.1 More on Bidirectional Bus
296(1)
7.2.1.2 Asynchronous SRAM
297(6)
7.2.2 Read-Only Memory
303(3)
7.3 Architecture Design and Timing Diagram
306(13)
7.3.1 Complex Multiplier
307(5)
7.3.2 Two Additions
312(2)
7.3.3 Finite Impulse Response Filter
314(5)
7.4 Digital Design of Huffman Coding
319(17)
7.4.1 Block Diagram and Interface
324(1)
7.4.2 Algorithm Design
325(3)
7.4.3 RTL Design
328(8)
7.5 Further Reading
336(25)
Problems
337(24)
Chapter 8 Advanced System Designs
361(80)
8.1 Dynamic Random-Access Memory
361(2)
8.2 Flash Memory
363(1)
8.3 Synchronizer Design
363(28)
8.3.1 Synchronization Failure
363(1)
8.3.2 Metastability
364(5)
8.3.3 Probability of Entering an Illegal State
369(1)
8.3.4 Simple Synchronizer
370(6)
8.3.5 Deterministic Multi-Bit Synchronizer
376(4)
8.3.6 Nondeterministic Multi-Bit Synchronizer Using FIFO without Flow Control
380(7)
8.3.7 Nondeterministic Multi-Bit Synchronizer Using FIFO with Flow Control
387(4)
8.4 Computer Organization
391(27)
8.4.1 Embedded Processor
391(3)
8.4.2 Instructions and Data
394(1)
8.4.3 Crypto Processor
394(1)
8.4.3.1 AES Algorithm
395(4)
8.4.3.2 Processor Design
399(4)
8.4.3.3 RTL Design
403(11)
8.4.3.4 AES in Assembly
414(4)
8.5 Digital Design of Component Labeling Engine
418(15)
8.5.1 Block Diagram and Interface
419(1)
8.5.2 Algorithm Design
419(6)
8.5.3 RTL Design
425(8)
8.6 Further Reading
433(8)
Problems
435(6)
Chapter 9 I/O Interface
441(50)
9.1 I/O Controller
441(12)
9.1.1 Simple Processor
445(1)
9.1.1.1 RTL Design
446(5)
9.1.1.2 I/O Control Program in Assembly
451(2)
9.2 Buses
453(3)
9.2.1 Multiplexed Buses
453(1)
9.2.2 Tristate Buses
454(1)
9.2.3 Open-Drain Buses
455(1)
9.3 Serial Transmission Techniques
456(4)
9.3.1 Serial Transmission Protocols
456(2)
9.3.2 Timing Synchronization
458(2)
9.4 I/O Interface of Embedded Software
460(10)
9.4.1 Polling
460(1)
9.4.2 Interrupts
461(1)
9.4.2.1 Simple Processor with Interrupt
462(2)
9.4.2.2 Keypad I/O Controller with Interrupt
464(2)
9.4.2.3 Program with Interrupt in Assembly for Two I/O Controls
466(2)
9.4.3 Timer
468(2)
9.5 Accelerators
470(18)
9.6 Further Reading
488(3)
Problems
489(2)
Chapter 10 Logic Synthesis with Design Compiler
491(54)
10.1 Design for Synthesis
491(2)
10.2 Design Flow Considering Synthesis
493(13)
10.2.1 Design Objects
494(1)
10.2.2 Reading Design
495(1)
10.2.3 Describing Design Environment
496(3)
10.2.4 Reporting and Analyzing Design
499(1)
10.2.4.1 Design Report
499(1)
10.2.4.2 Timing Report
500(3)
10.2.4.3 Area Report
503(1)
10.2.4.4 Power Report
504(1)
10.2.5 Saving Design
505(1)
10.3 Setting Design Constraints
506(14)
10.3.1 Optimization Constraints
506(1)
10.3.1.1 Creating Clock
506(1)
10.3.1.2 Clock Latency
507(1)
10.3.1.3 Clock Transition
508(1)
10.3.1.4 Clock Uncertainty
509(1)
10.3.1.5 Impacts of Clock Tree Modeling
510(2)
10.3.1.6 More on Impacts of Clock Tree Modeling
512(1)
10.3.1.7 Derived Clock
513(2)
10.3.1.8 Multiple Clock Design
515(1)
10.3.1.9 Propagated Clock after CTS
516(1)
10.3.1.10 Maximum Delay of a Combinational Circuit
517(1)
10.3.1.11 Timing Exceptions
518(2)
10.3.2 Design Rule Constraints
520(1)
10.4 Compiling Design
520(16)
10.4.1 Timing Optimization
520(2)
10.4.2 Area Optimization
522(1)
10.4.3 Power Optimization
523(1)
10.4.3.1 Power Model
523(2)
10.4.3.2 Clock Gating
525(2)
10.4.3.3 Dynamic Power Optimization
527(2)
10.4.3.4 Power Analysis
529(1)
10.4.4 Mapping Effort
530(1)
10.4.5 Solving Setup Time Violations
531(1)
10.4.6 Solving Hold Time Violations
532(1)
10.4.7 Solving Multiple Port Nets
532(2)
10.4.8 Solving Large For Loops
534(2)
10.4.9 Solving Naming Rules
536(1)
10.5 Adaptive Threshold Engine
536(4)
10.6 Further Reading
540(5)
Problems
541(4)
Appendix A Basic Logic Gates and User Defined Primitives
545(14)
A.1 Basic Logic Gates
545(8)
A.2 User Defined Primitives
553(4)
A.3 Further Reading
557(2)
Appendix B Non-Synthesizable Constructs
559(4)
B.1 Non-Synthesizable Verilog Statements
559(3)
B.2 Further Reading
562(1)
Appendix C Advanced Net Data Types
563(4)
C.1 Examples
563(2)
C.2 Further Reading
565(2)
Appendix D Signed Multipliers
567(4)
D.1 Synthesis of Signed Multipliers
567(3)
D.2 Further Reading
570(1)
Appendix E Design Principles and Guidelines
571(14)
E.1 Basic Principles
571(2)
E.2 Design Guidelines
573(9)
E.3 Other Coding and Naming Styles
582(2)
E.4 Further Reading
584(1)
Index 585
Wen-Long Chin is a professor of Engineering Science, at the National Cheng Kung University (NCKU), Taiwan. Before holding the faculty position, he worked in the Hsinchu Science Park, Taiwan, for over 11 years, in charge of communication and network IC designs. He is a senior member of IEEE and serves as Technical Editor of IEEE Wireless Communications, and Associate Editors of IEEE Access and EURASIP Journal on Wireless Communications and Networking. He has published approximately 60 Journal and conference papers, 1 book chapter, and 14 patents.