Proceedings of the 1999 7th International Symposium on the Physical & Failure Analysis of Integrated Circuits [ ipfa '99: 5-9 July, 1999, Orchard Hotel, Singapore] 1999, 7th International ed. [Mikrofilm]

Impact of New Materials, Changes in Physics and Continued ULSI Scaling on Failure Mechanisms and Analysis 1(9) Y. Nishi J. W. McPherson Session 1: Failure Analysis Techniques I J.C.H. Phang Invited Paper Can Failure Analysis Keep Peace with IC Technology Development? 9(6) C. Boit Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors 15(6) W.M. Yee M. Paniccia T. Eiles V.R.M. Rao Session 2: Process and Device W.K. Choi Influence of Passivation Anneal Position on Metal Coverage Dependent Mismatch and Hot Carrier Reliability 21(4) S. Chetlur. S. Sen E. Harris H. Vaidya I. Kizilyalli R. Gregor B. Harding The Effect of Nitrogen Pre-Annealing on the Sidewall Oxidation of WSix and on the Related Electrical Properties of WSix/Poly Si Gate Structure 25(5) D.H Kang H.S. Kim M.J. Chung K.H. Ahn S.T. Chung K.W. Park G.S. Cho J.B. Park Y.H. Koh Radiation-Induced Leakage Current of Ultra-thin Gate Oxide Under X-ray Lithography Conditions 30(4) B.J. Cho S.J. Kim C.H. Ling M.S. Joo I.S. Yeo Excellent Quality Ultra-Thin Oxides Prepared by Room Temperature Anodic Oxidation 34(5) J.S. Liu M.C. Chiang C.L. Chen T.Y. Huang Session 3: Packaging and Metallization I S.H. Ong Impact of Test Structure Design on Electromigration of Metal Interconnect 39(5) Q. Guo K.F. Lo X. Zeng P. Yao S.P. Neo Impact of Voids in Ti-Salicided p+ Polysilicon Lines on TiSi2 Electrical Properties 44(6) H.N. Chua K.L. Pey S.Y. Siah L.Y. Ong E.H. Lim C.L. Gan K.H. See C.S. Ho Detection of Underfill Epoxy Defects in Flip Chip Packages with the Aid of SAM, Parallel Polishing & FIB 50(5) T.N. Tang H.C. Heng S.Y. Chan M. Hiew Monte Carlo Simulation of Electromigration in Polycrystalline Metal Stripes 55(5) S. Di Pascoli G. Iannaccone Impact of Intermetal Dielectric Process on Al Via Electromigration Reliability 60(4) X. Liu K.F. Lo K.Y. Chin Q. Guo G.L. Teh Session 4: Failure Analysis Techniques II J.T.L. Thong Failure Analysis of μBGA - New Approaches in Fault Isolation 64(5) S.H. Kuan S.T. Teh New FIB-Supported Approaches for EELS-Capable TEM-Lamella Preparation 69(4) P. Jacob A. Schertel L. Peto G. Sundaram# Illumination-Sensitive Failure Mechanism - A Case Study on Transient Icc Failure 73(4) S.T. Teh W.Y. Teoh Session 5: Dielectrics I D.J. Dumin Origin of the Substrate Current After Soft-Breakdown in Thin Oxide n-MOSFETs 77(4) F. Crupi G. Iannaccone B. Neri I. Crupi R. Degraeve G. Groeseneken H.E. Maes A Study of Quasi-Breakdown Mechanism in Ultra-Thin Gate Oxide by Using DCIV Technique 81(4) H. Guan B.J. Cho M.F. Li Y.D. He Z. Xu Z. Dong A Detailed Analysis of the Pre-Breakdown Current Fluctuations in Thin Oxide MOS Capacitors 85(4) B. Neri F. Crupi G. Basso S. Lombardo Session 6: Hot-Carrier I G. Groeseneken A New DC Voltage-Voltage Method to Measure the Interface Traps in Deep Sub-Micron MOS Transistors 89(5) B.B. Jie M.F. Li W.K. Chim D.S.H. Chan K.F. Lo Channel-Width Effect on Hot-Carrier Degradation in NMOSFETs with Recessed-LOCOS Isolation Structures 94(5) J.M.P. Yue W.K. Chim B.J. Cho D.S.H. Chan W.H. Qin Y.B. Kim S.A.Jang I.S. Yeo Series Resistance and Effective Channel Mobility Degradation in LDD NMOSFETs Under Hot-Carrier Stressing 99(5) G.G. Oh W.K. Chim D.S.H. Chan C.L. Lou Session 7: Failure Analysis Techniques III Y.K. Swee Automatic DRAM Cell Location in the SEM 104(4) J.T.L Thong Y. Zhu J.C.H. Phang Characterization and Application of Highly-Sensitive Infra-Red Emission Microscopy for Microprocessor Backside Failure Analysis 108(5) T.H. Loh W.M. Yee Y.Y. Chew An Integrated (Automated) Photon Emission Microscope and MOSFET Characterization System for Combined Microscopic and Macroscopic Device Analysis 113(6) T.H. Ng W.K. Chim D.S.H. Chan J.C.H. Phang Y.Y. Liu C.L. Lou S.E. Leang J.M. Tao Novel Backside Sample Preparation Processes for Advanced CMOS Integrated Circuits Failure Analysis 119(4) Y.Y. Chew K.H. Siek W.M. Yee Session 8: Packaging and Metallization II R. Mehta Impact of Failure Criteria on Electromigration of W-plug Contact 123(5) Q. Guo K.F. Lo X, Zeng X. Liu P. Yao P.Y. Tan Identification of Processing Defects by Focused Ion Beam (FIB) Induced Voltage Contrast 128(4) C.S. Liu C.R. Chen Y.F. Hsieh Long Term Noise Measurements to Characterize Electromigration in Metal Lines of ICs 132(4) C. Ciofi V. Dattilo B. Neri S. Foley A. Mathewson Session 9: Dielectrics II D.S.H. Chan An Empirical Breakdown Model of the Gate Oxide Under Current Stress 136(4) J.H. Seo J.C.S. Woo A Comparison of Interface Trap Generation by Fowler-Nordheim Electron Injection and Hot-Hole Injection Using the DCIV Method 140(5) K.H. Ng B.B. Jie Y.D. He W.K. Chim M.F. Li K.F. Lo The Electric Field, Oxide Thickness, Time and Fluence Dependences of Trap Generation in Silicon Oxides and Their Support of the E-Model of Oxide Breakdown 145(6) D. Qian D.J. Dumin Session 10: EOS/ESD and Latchup C. Duvvury A Novel Dual-Direction IC ESD Protection Device 151(5) A.Z. Wang C.H. Tsay Q.W. Shan Latent Damage Investigation on Lateral Non-Uniform Charge Generation and Stress-Induced Leakage Current in Silicon Dioxides Subjected to Low-Level Electrostatic Discharge Impulse Stressing 156(6) P.S. Lim W.K. Chim An Analytical Model of Positive H.B.M. ESD Current Distribution and the Modified Multi-Finger Protection Structure 162(6) J.H. Lee J.R. Shih Y.H. Wu B.K. Liew H.L. Hwang A Latch-up Immunized Lateral Trench-Gate Conductivity Modulated Power Transistor 168(5) J. Cai K.F. Lo J.K.O. Sin Session 11: Physical Analysis and Reliability of Specialist Devices K.L. Pey Invited Paper Physical Analysis and Modeling of the Reliability of AlGaAs/GaAs HBTs 173(7) J.J. Liou A.A. Rezazadeh Study on LED Degradation Using CL, EBIC and a Two-Diode Parameter Extraction Model 180(5) H. Xiao Y.Y, Liu J.C.H. Phang D.S.H. Chan W.K. Chim K.P. Yan Temperature Distribution in Power GaAs Field Effect Transistors Using Spatially Resolved Photoluminescence Mapping 185(6) J.P. Landesman E. Martin P. Braun Analysis of Surface-State Effects on Gate-Lag Phenomena in Recessed-Gate and Buried-Gate GaAs MESFETs 191(4) K. Horio A. Wakabayashi T. Yamada Session 12: Hot-Carrier II C. Yang Low-Voltage Forward Gated Diode: An Early Monitor of Hot-Carrier Degradations in Scaled MOSFETs 195(5) M.J. Chen T.K. Kang A Comparative Study of Charge Trapping Effects in LDD Surface-Channel and Buried-Channel PMOS Transistors Using Charge Profiling and Threshold Voltage Shift Measurements 200(6) C.K. Kok W.C. Chew W.K. Chim D.S.H. Chan S.E. Leang Energy Dependence of Interface Trap Density - Investigated by the DCIV Method 206 B.B. Jie M.F. Li K.F. Lo