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Processor Design: System-On-Chip Computing for ASICs and FPGAs 2007 ed. [Kõva köide]

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  • Formaat: Hardback, 526 pages, kõrgus x laius: 235x155 mm, kaal: 980 g, XX, 526 p., 1 Hardback
  • Ilmumisaeg: 27-Jun-2007
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1402055293
  • ISBN-13: 9781402055294
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  • Formaat: Hardback, 526 pages, kõrgus x laius: 235x155 mm, kaal: 980 g, XX, 526 p., 1 Hardback
  • Ilmumisaeg: 27-Jun-2007
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1402055293
  • ISBN-13: 9781402055294
Teised raamatud teemal:
Here is an extremely useful book that provides insight into a number of different flavors of processor architectures and their design, software tool generation, implementation, and verification. After a brief introduction to processor architectures and how processor designers have sometimes failed to deliver what was expected, the authors introduce a generic flow for embedded on-chip processor design and start to explore the vast design space of on-chip processing. The authors cover a number of different types of processor core.

Processor Design addresses the design of different types of embedded, firmware-programmable computation engines. Because the design and customization of embedded processors has become a mainstream task in the development of complex SoCs (Systems-on-Chip), ASIC and SoC designers must master the integration and development of processor hardware as an integral part of their job. Even contemporary FPGA devices can now accommodate several programmable processors. There are many different kinds of embedded processor cores available, suiting different kinds of tasks and applications.Processor Design provides insight into a number of different flavors of processor architectures and their design, software tool generation, implementation, and verification. After a brief introduction to processor architectures and how processor designers have sometimes failed to deliver what was expected, the authors introduce a generic flow for embedded on-chip processor design and start to explore the vast design space of on-chip processing. The types of processor cores covered include general purpose RISC cores, traditional DSP, a VLIW approach to signal processing, processor cores that can be customized for specific applications, reconfigurable processors, protocol processors, Java engines, and stream processors. Co-processor and multi-core design approaches that deliver application-specific performance over and above that which is available from single-core designs are also described. The special design requirements for processors targeted for FPGA implementation, clock generation and distribution in microprocessor circuits, and clockless realization of processors are addressed. Tools and methodologies for application-specific embedded processor design are covered, together with processor modelling and early estimation techniques, and programming tool support for custom processors. The book concludes with a glance to the future of embedded on-chip processors.

Arvustused

From the reviews:

Editor Jari Nurmis proposal was to put together the first effective textbook aimed at the subject of processor design. The book comprises 21 chapters, written by a total of 45 contributing authors with backgrounds in both academic and industrial fields. To summarize, this book offers a nice overview on the steps involved in designing a soft-processor, as well as a good perspective on past architectures and current trends in processor design. (Ricardo Jasinski, The Computer Journal, Vol. 53 (1), 2010)

List of Contributing Authors xv
1 Introduction
1
2 Embedded Computer Architecture Fundamentals
7
Components of (an embedded) computer
7
Architecture organization
12
Ways of parallelism
15
Memory
19
I/O operations and peripherals
26
3 Beyond the Valley of the Lost Processors: Problems, Fallacies, and Pitfalls in Processor Design
27
Designing a high-level computer instruction-set architecture (ISA) to support a specific language or language domain
28
Use of intermediate ISAs to allow a simple machine to emulate its betters
32
Stack machines
35
Extreme CISC and extreme RISC
39
Very long instruction word (VLIW)
43
Overly aggressive pipelining
45
Unbalanced processor design
47
Omitting pipeline interlocks
50
Non-power-of-2 data-word widths for general-purpose computing
53
Too small an address space
55
Memory segmentation
58
Multithreading
60
Symmetric multiprocessing
63
4 Processor Design Flow
69
Capturing requirements
69
Instruction coding
74
Exploration of architecture organizations
79
Hardware and software development
80
Software tools and libraries
82
5 General-Purpose Embedded Processor Cores — The COFFEE RISC Example
83
Introduction
83
Implications of RISC design philosophy
84
The COFFEE RISC Core instruction set architecture
86
Software view of the COFFEE RISC Core
88
Hardware view of the COFFEE RISC Core
90
The COFFEE RISC Core pipeline structure
92
The COFFEE RISC Core implementation
95
The COFFEE RISC Core characteristics
97
Conclusions
100
6 The DSP and Its Impact on Technology
101
Introduction
101
Why a DSP is different
105
The evolving architecture of a DSP
113
What is next in the evolution of the DSP
115
Summary
119
7 VLIW DSP Processor for High-End Mobile Communication Applications
121
Trends in mobile communication
122
DSP-specific requirements
124
Microarchitectural concepts
126
VLIW and SW programmability
128
3a, an application specific adaptable core architecture
130
Benchmarking: kernel versus application benchmarking
139
Design space exploration
142
The complexity of configurability
145
Summary
147
Acknowledgment
148
8 Customizable Processors and Processor Customization
149
Introduction
149
A benefits analysis of processor customization
150
Using microprocessor cores in SOC design
153
Benefiting from microprocessor extensibility
154
How microprocessor use differs between SOC and board-level design
157
Tensilica's extensible Xtensa processor core
162
The TIE language
169
Conclusion
175
9 Run-Time Reconfigurable Processors
177
Embedded microprocessor trends
178
Instruction set metamorphosis
180
Reconfigurable computing
184
Run-time reconfigurable instruction set processors
186
Coarse-grained reconfigurable processors
196
Conclusions
205
10 Coprocessor Approach to Accelerating Multimedia Applications 209
Need for accelerators
209
Accelerators and different types of parallelism
210
Processor architectures and different approaches to acceleration
211
Requirements of applications for hardware coprocessors
212
Numeric coprocessors: floating-point units
214
Various types of reconfigurable accelerators
215
Milk coprocessor and Butter accelerator
217
Conclusions
226
11 Designing Soft-Core Processors for FPGAs 229
Configurable processors
230
Challenges of FPGA processor design
231
Opportunities of FPGA processor design
232
FPGA architecture overview
234
FPGA design issues
238
Instruction set issues
246
FPGA processor instruction set comparison
249
Case study – Nios II
250
Closing comments
255
Acknowledgments
256
12 Protocol Processor Design Issues 257
Introduction
257
Domain and application analysis for optimized protocol processing hardware
259
Hardware abstraction to handle the complexity of specifications
262
Custom design frameworks
264
Design processes
266
The TACO framework for protocol processor design
268
Conclusions
284
13 Java Co-Processor for Embedded Systems 287
Introduction
287
Generic virtual machine architecture
288
Using hardware systems in virtual machine implementations
290
Structure of the co-processor
291
Current status and future work
307
Summary
308
14 Stream Multicore Processors 309
Introduction
309
Raw architecture overview
315
Related architectures
319
Raw chip implementation
322
Methodology for performance analysis
324
Stream computation
328
ILP computation
333
Bit-level computation
335
Conclusion
337
Acknowledgments
338
15 Processor Clock Generation and Distribution 339
Introduction
339
Clock parameters and trends
340
Clock distribution networks
344
Deskew circuits
350
Jitter reduction techniques
354
Low power clock distribution
356
Future directions in clock distribution
360
Summary
366
16 Asynchronous and Self-Timed Processor Design 367
Motivation for asynchronous design
367
The development of asynchronous processors
370
Asynchronous design styles
373
Features of asynchronous design
376
Summary and conclusions
388
17 Early-Estimation Modeling of Processors 391
Introduction
391
History of early estimation models for computer architectures
392
Adapting models to meet modern processor architectures
394
Architecture modeling
395
Processor logic optimization at 90 nm technology
400
Physical design issues in the era of sub-100 nm technologies
403
18 System Level Simulations 405
Introduction
405
Simulation and languages
411
TACO configurable SystemC simulator
415
High-level instruction set simulator generator for COFFEE Risc Core
422
Conclusion
425
19 Programming Tools for Reconfigurable Processors 427
Algorithm development on reconfigurable processors (programming issues)
428
Instruction set extension implementation on a standard compilation tool-chain
430
Bridging the gap from hardware to software through C-described data flow graphs
434
Overview of programming tools for reconfigurable processors
437
An example of algorithm development environment for reconfigurable processors: the Griffy-C approach
439
20 Software-Based Self-Testing of Embedded Processors 447
Evolution of software-based self-test
452
High-level SBST methodology
463
Case studies – experimental results
476
Conclusions and perspective
481
21 Future Directions in Processor Design 483
References 487
Index 515


Dr. Jari Nurmi is Professor at Tampere University of Technology and his expertises lie in: DSP Processor Architecture, Network-on-Chip, Embedded System-on-Chip Design, Integrated Signal Processing and Digital Communication Circuits.



Jari Nurmi has edited one successful book for Springer.