List of Contributing Authors |
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2 Embedded Computer Architecture Fundamentals |
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7 | |
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Components of (an embedded) computer |
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7 | |
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Architecture organization |
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12 | |
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15 | |
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19 | |
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I/O operations and peripherals |
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26 | |
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3 Beyond the Valley of the Lost Processors: Problems, Fallacies, and Pitfalls in Processor Design |
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27 | |
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Designing a high-level computer instruction-set architecture (ISA) to support a specific language or language domain |
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28 | |
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Use of intermediate ISAs to allow a simple machine to emulate its betters |
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32 | |
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35 | |
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Extreme CISC and extreme RISC |
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39 | |
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Very long instruction word (VLIW) |
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43 | |
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Overly aggressive pipelining |
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45 | |
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Unbalanced processor design |
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47 | |
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Omitting pipeline interlocks |
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50 | |
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Non-power-of-2 data-word widths for general-purpose computing |
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53 | |
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Too small an address space |
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55 | |
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58 | |
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60 | |
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Symmetric multiprocessing |
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63 | |
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69 | |
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69 | |
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74 | |
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Exploration of architecture organizations |
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79 | |
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Hardware and software development |
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80 | |
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Software tools and libraries |
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82 | |
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5 General-Purpose Embedded Processor Cores — The COFFEE RISC Example |
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83 | |
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83 | |
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Implications of RISC design philosophy |
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84 | |
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The COFFEE RISC Core instruction set architecture |
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86 | |
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Software view of the COFFEE RISC Core |
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88 | |
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Hardware view of the COFFEE RISC Core |
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90 | |
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The COFFEE RISC Core pipeline structure |
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92 | |
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The COFFEE RISC Core implementation |
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95 | |
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The COFFEE RISC Core characteristics |
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97 | |
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100 | |
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6 The DSP and Its Impact on Technology |
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101 | |
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101 | |
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105 | |
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The evolving architecture of a DSP |
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113 | |
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What is next in the evolution of the DSP |
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115 | |
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119 | |
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7 VLIW DSP Processor for High-End Mobile Communication Applications |
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121 | |
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Trends in mobile communication |
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122 | |
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DSP-specific requirements |
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124 | |
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Microarchitectural concepts |
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126 | |
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VLIW and SW programmability |
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128 | |
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3a, an application specific adaptable core architecture |
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130 | |
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Benchmarking: kernel versus application benchmarking |
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139 | |
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142 | |
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The complexity of configurability |
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145 | |
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147 | |
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148 | |
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8 Customizable Processors and Processor Customization |
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149 | |
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149 | |
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A benefits analysis of processor customization |
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150 | |
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Using microprocessor cores in SOC design |
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153 | |
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Benefiting from microprocessor extensibility |
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154 | |
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How microprocessor use differs between SOC and board-level design |
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157 | |
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Tensilica's extensible Xtensa processor core |
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162 | |
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169 | |
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175 | |
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9 Run-Time Reconfigurable Processors |
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177 | |
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Embedded microprocessor trends |
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178 | |
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Instruction set metamorphosis |
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180 | |
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184 | |
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Run-time reconfigurable instruction set processors |
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186 | |
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Coarse-grained reconfigurable processors |
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196 | |
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205 | |
10 Coprocessor Approach to Accelerating Multimedia Applications |
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209 | |
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209 | |
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Accelerators and different types of parallelism |
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210 | |
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Processor architectures and different approaches to acceleration |
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211 | |
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Requirements of applications for hardware coprocessors |
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212 | |
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Numeric coprocessors: floating-point units |
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214 | |
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Various types of reconfigurable accelerators |
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215 | |
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Milk coprocessor and Butter accelerator |
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217 | |
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226 | |
11 Designing Soft-Core Processors for FPGAs |
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229 | |
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230 | |
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Challenges of FPGA processor design |
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231 | |
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Opportunities of FPGA processor design |
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232 | |
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FPGA architecture overview |
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234 | |
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238 | |
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246 | |
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FPGA processor instruction set comparison |
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249 | |
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250 | |
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255 | |
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256 | |
12 Protocol Processor Design Issues |
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257 | |
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257 | |
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Domain and application analysis for optimized protocol processing hardware |
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259 | |
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Hardware abstraction to handle the complexity of specifications |
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262 | |
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264 | |
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266 | |
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The TACO framework for protocol processor design |
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268 | |
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284 | |
13 Java Co-Processor for Embedded Systems |
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287 | |
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287 | |
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Generic virtual machine architecture |
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288 | |
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Using hardware systems in virtual machine implementations |
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290 | |
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Structure of the co-processor |
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291 | |
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Current status and future work |
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307 | |
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308 | |
14 Stream Multicore Processors |
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309 | |
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309 | |
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Raw architecture overview |
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315 | |
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319 | |
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322 | |
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Methodology for performance analysis |
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324 | |
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328 | |
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333 | |
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335 | |
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337 | |
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15 Processor Clock Generation and Distribution |
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339 | |
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339 | |
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Clock parameters and trends |
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340 | |
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Clock distribution networks |
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344 | |
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350 | |
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Jitter reduction techniques |
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354 | |
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Low power clock distribution |
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356 | |
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Future directions in clock distribution |
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360 | |
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366 | |
16 Asynchronous and Self-Timed Processor Design |
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367 | |
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Motivation for asynchronous design |
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367 | |
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The development of asynchronous processors |
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370 | |
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Asynchronous design styles |
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373 | |
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Features of asynchronous design |
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376 | |
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388 | |
17 Early-Estimation Modeling of Processors |
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391 | |
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391 | |
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History of early estimation models for computer architectures |
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392 | |
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Adapting models to meet modern processor architectures |
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394 | |
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395 | |
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Processor logic optimization at 90 nm technology |
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400 | |
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Physical design issues in the era of sub-100 nm technologies |
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403 | |
18 System Level Simulations |
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405 | |
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405 | |
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411 | |
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TACO configurable SystemC simulator |
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415 | |
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High-level instruction set simulator generator for COFFEE Risc Core |
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422 | |
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425 | |
19 Programming Tools for Reconfigurable Processors |
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427 | |
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Algorithm development on reconfigurable processors (programming issues) |
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428 | |
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Instruction set extension implementation on a standard compilation tool-chain |
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430 | |
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Bridging the gap from hardware to software through C-described data flow graphs |
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434 | |
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Overview of programming tools for reconfigurable processors |
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437 | |
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An example of algorithm development environment for reconfigurable processors: the Griffy-C approach |
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439 | |
20 Software-Based Self-Testing of Embedded Processors |
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Evolution of software-based self-test |
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452 | |
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High-level SBST methodology |
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463 | |
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Case studies – experimental results |
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476 | |
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Conclusions and perspective |
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481 | |
21 Future Directions in Processor Design |
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483 | |
References |
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487 | |
Index |
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