In response to semiconductor fabrication scaling, the proceedings of the March 2005 symposium examines device modeling, circuits, and architectures for building robust systems with increasingly variable and leaky transistors. The 83 papers and 23 posters focus on the improvement of design quality, particularly with respect to metrics such as yield, testability, design productivity, and overall systems cost. Topics include noise library characterization for static noise analysis tools, an electromigration reliability comparison of Cu and Al interconnects, statistical analysis of clock skew variation in H-tree structure, and reticle floor planning and wafer dicing for multiple project wafers. No subject index is provided. Annotation ©2004 Book News, Inc., Portland, OR (booknews.com)
