Muutke küpsiste eelistusi

Reconfigurable Networks-on-Chip 2012 [Kõva köide]

, , ,
  • Formaat: Hardback, 206 pages, kõrgus x laius: 235x155 mm, kaal: 500 g, XIV, 206 p., 1 Hardback
  • Ilmumisaeg: 15-Dec-2011
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1441993401
  • ISBN-13: 9781441993403
Teised raamatud teemal:
  • Kõva köide
  • Hind: 95,02 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Tavahind: 111,79 €
  • Säästad 15%
  • Raamatu kohalejõudmiseks kirjastusest kulub orienteeruvalt 2-4 nädalat
  • Kogus:
  • Lisa ostukorvi
  • Tasuta tarne
  • Tellimisaeg 2-4 nädalat
  • Lisa soovinimekirja
Reconfigurable Networks-on-Chip 2012Suurem pilt
  • Formaat: Hardback, 206 pages, kõrgus x laius: 235x155 mm, kaal: 500 g, XIV, 206 p., 1 Hardback
  • Ilmumisaeg: 15-Dec-2011
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1441993401
  • ISBN-13: 9781441993403
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781441993403.html
Märksõnad:
Providing a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip (NoC), this book addresses a wide spectrum of on-chip communication problems. It offers practical knowledge about the design and implementation of NoC.

This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation. Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC. From the Foreword:Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers.--Giovanni De Micheli

Arvustused

From the reviews:

This monograph reviews the fundamental theories, architectures, algorithms, and state-of-the-art development of NoC. The book begins with an overview of the communication-centric design for multi-processor system-on-chip (MP-SoC) and conventional NoC architectures, followed by an extended introduction to the design methodology of NoC. The book concludes with a case study of bidirectional NoC (BiNoC) architecture. Overall, this monograph provides an in-depth, academic introduction to the design methodology of NoC architecture. It is suitable for academic researchers and professionals working with NoC. (Jun Liu, ACM Computing Reviews, July, 2012)

Part I Introduction to Network-on-Clip
1 Communication Centric Design
3(12)
1.1 Communications-Centric Design Concept
3(3)
1.1.1 Multi-Processor System-on-Chip
4(1)
1.1.2 Conventional on-Chip Communication Scheme
4(1)
1.1.3 Emergence of Network-on-Chip
5(1)
1.2 Concept of Network-on-Chip
6(1)
1.3 Layers in a Network-on-Chip Design
6(2)
1.3.1 Physical Layer
7(1)
1.3.2 Network Layer
7(1)
1.3.3 Application Layer
8(1)
1.4 Motivation and Contributions
8(3)
1.4.1 Motivation
9(1)
1.4.2 Contributions
9(2)
1.5 Organization of Book
Chapters
11(1)
References
11(4)
2 Preliminaries
15(20)
2.1 Background Knowledge
15(1)
2.2 Conventional Network-on-Chip Architecture
16(1)
2.3 Conventional Router Architecture
17(1)
2.4 Flow-Control Mechanism
18(3)
2.4.1 Packet-Buffer Flow-Control
19(1)
2.4.2 Wormhole Flow-Control Based Router
19(1)
2.4.3 Virtual-Channel Flow-Control Based Router
20(1)
2.5 Routing and Arbitration Techniques
21(2)
2.5.1 Problem Decomposition
22(1)
2.5.2 State-of-the-Art
22(1)
2.6 Quality-of-Service Control
23(2)
2.6.1 Connection-Oriented Scheme
24(1)
2.6.2 Connection-Less Scheme
24(1)
2.7 Reliability Design
25(2)
2.7.1 Failure Types in NoC
25(1)
2.7.2 Reliability Design in NoC
26(1)
2.8 Energy-Aware Task Scheduling
27(1)
References
28(7)
Part II Network-on-Chips Design Methodologies Exploration
3 Techniques for High Performance Noc Routing
35(16)
3.1 NoC Routing Basics
35(3)
3.1.1 Characterization of NoC Routing
35(1)
3.1.2 Deadlock and Livelock Issues
36(1)
3.1.3 Deadlock-Free Routing Schemes in NoCs
36(2)
3.2 Turn Model Based Routing Basics
38(2)
3.2.1 Odd-Even Turn Model
38(1)
3.2.2 Odd-Even Turn-Model Based Routing Algorithm, ROUTE
38(1)
3.2.3 Motivations of our Proposed Turn Model Based Routing Schemes
39(1)
3.3 Proposed Turn-Model Based Fully Adaptive Routing
40(9)
3.3.1 Turn Prohibitions Release
40(1)
3.3.2 Path Prohibitions Release
41(2)
3.3.3 Deadlock Freedom and Livelock Freedom
43(1)
3.3.4 Fault Tolerance Advantage
44(2)
3.3.5 Performance Evaluation
46(3)
3.4 Remarks
49(1)
References
49(2)
4 Performance-Energy Tradeoffs for Noc Reliability
51(18)
4.1 Reliability in NoC
51(2)
4.2 State-of-the-Art Reliable NoC
53(1)
4.3 Fault Modeling
54(1)
4.4 Energy Consumption in an NoC Architecture
55(3)
4.4.1 Derivation of Energy Metrics
56(1)
4.4.2 Effect of Retransmission Buffer
56(1)
4.4.3 Re-Calculation of Energy per Useful Bit
57(1)
4.5 Experimental Results
58(7)
4.5.1 Experiments Setup
58(1)
4.5.2 Error Control Codes used in Experiments
59(1)
4.5.3 Results Analysis
60(5)
4.6 Remarks
65(1)
References
66(3)
5 Energy-Aware Task Scheduling for Noc-Based DVS System
69(22)
5.1 Problem Formulation
69(4)
5.1.1 Application and Architecture Specification
70(1)
5.1.2 Generalized Energy-Aware Task Scheduling Problem
71(1)
5.1.3 Dynamic Voltage Scaling
72(1)
5.2 Motivational Example
73(2)
5.3 Proposed Algorithmic Solution
75(9)
5.3.1 Task Prioritization
76(1)
5.3.2 Task Assignment
77(1)
5.3.3 Power Optimization
78(3)
5.3.4 Re-Scheduling Setup
81(3)
5.4 Experimental Results
84(3)
5.5 Remarks
87(1)
References
88(3)
Part III Case Study: Bidirectional NoC (BiNoC) Architecture
6 Bidirectional Noc Architecture
91(46)
6.1 Problem Description
91(4)
6.1.1 Motivational Example
92(1)
6.1.2 Channel Bandwidth Utilization
93(2)
6.2 Bidirectional Channel
95(1)
6.2.1 Design Requirements
95(1)
6.2.2 Related Works
96(1)
6.3 BiNoC: Bidirectional NoC Router Architecture
96(6)
6.3.1 BiNoC Router with Wormhole Flow-Control
96(2)
6.3.2 BiNoC Router with Virtual-Channel Flow-Control
98(1)
6.3.3 Reconfigurable Input/Output Ports
98(2)
6.3.4 Channel Control Module
100(1)
6.3.5 Virtual-Channel Allocator
100(1)
6.3.6 Switch Allocator
101(1)
6.4 Bidirectional Channel Direction Control
102(10)
6.4.1 Inter-Router Transmission Scheme
102(1)
6.4.2 Bidirectional Channel Routing Direction Control
103(3)
6.4.3 Resource Contention
106(4)
6.4.4 Packet Ordering
110(1)
6.4.5 Packet Transmission Interruption
111(1)
6.5 BiNoC Characterization
112(21)
6.5.1 Experiments Setup
113(1)
6.5.2 Synthetic Traffic Analysis
114(8)
6.5.3 Experiments with Real Applications
122(1)
6.5.4 Implementation Details in Terms of Area and Power
123(6)
6.5.5 Implementation Overhead
129(4)
6.6 Remarks
133(1)
References
134(3)
7 Quality-of-Service in BiNoc
137(20)
7.1 QoS Control in NoC
137(1)
7.2 Typical Connection-Less QoS Mechanism for NoC
138(1)
7.3 Motivational Example
138(2)
7.4 QoS Design for BiNoC Router
140(2)
7.4.1 Prioritized VC Management and Inter-Router Arbitration
140(1)
7.4.2 Prioritized Deadlock-Free Routing Restriction
141(1)
7.5 Inter-Router Transmission Scheme
142(1)
7.6 QoS Design for BiNoC Channel-Direction Control
143(3)
7.6.1 High-Priority FSM Operations
144(2)
7.6.2 Low-Priority FSM Operations
146(1)
7.7 Performance Evaluation
146(9)
7.7.1 Comparison Between BiNoC_QoS and BiNoC_4VC
147(2)
7.7.2 Comparison Between BiNoC_QoS and NoC_QoS
149(1)
7.7.3 Analysis of Prioritized Routing
149(3)
7.7.4 Analysis of Consumption Rate
152(1)
7.7.5 Comparison Between GS and BE Traffics
153(2)
7.8 Remarks
155(1)
References
155(2)
8 Fault Tolerance in BiNoC
157(16)
8.1 Problem and Motivation
157(1)
8.2 Fault-Tolerance Basics
158(2)
8.2.1 Fault Types in NoCs
158(1)
8.2.2 Fault-Tolerance in NoCs
158(1)
8.2.3 Bidirectional Channels in NoCs
159(1)
8.2.4 Problems of Existing Fault-Tolerant Schemes
159(1)
8.2.5 Methodology of our Proposed Scheme
160(1)
8.3 Proposed Bi-Directional Fault-Tolerant NoC Architecture
160(7)
8.3.1 Bidirectional Channels
161(1)
8.3.2 Bidirectional Router Architecture
161(1)
8.3.3 Channel Direction Change Handshaking
162(1)
8.3.4 Fault-Tolerance Control Procedure
163(1)
8.3.5 In-Router Deadlock and its Solution
164(1)
8.3.6 Failure Rate Enhancement
165(1)
8.3.7 Reliability Enhancement
166(1)
8.4 Experimental Results
167(3)
8.4.1 Experiments with Synthetic Traffics
167(2)
8.4.2 Experiments with Real Traffics
169(1)
8.4.3 Implementation Overhead
170(1)
8.5 Remarks
170(1)
References
170(3)
9 Energy-Aware Application Mapping for BiNoC
173(20)
9.1 Preliminaries
173(3)
9.1.1 Task and Communication Scheduling
174(1)
9.1.2 Communication Model of BiNoC Architecture
174(2)
9.2 Motivational Example
176(1)
9.3 Task and Communication Scheduling for BiNoC
177(10)
9.3.1 Communication Model and Traffic on BiNoC
178(3)
9.3.2 Performance Refinement Process
181(4)
9.3.3 Self-Study and Sieve Framework
185(2)
9.4 Proposed Power Optimization Solution
187(2)
9.4.1 Coarse-Grained Power Optimization
187(1)
9.4.2 Fine-Grained Power Optimization
187(1)
9.4.3 Proposed Power-Efficient Scheduling
188(1)
9.5 Experimental Results
189(2)
9.6 Remarks
191(1)
Reference
191(2)
10 Concluding Remarks
193(2)
Appendix A Simulation Environment 195(4)
Appendix B Performance Metrics 199(2)
Index 201