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RF-Frontend Design for Process-Variation-Tolerant Receivers 2012 ed. [Pehme köide]

  • Formaat: Paperback / softback, 180 pages, kõrgus x laius: 235x155 mm, kaal: 454 g, VIII, 180 p., 1 Paperback / softback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 12-Apr-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1493902237
  • ISBN-13: 9781493902231
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  • Formaat: Paperback / softback, 180 pages, kõrgus x laius: 235x155 mm, kaal: 454 g, VIII, 180 p., 1 Paperback / softback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 12-Apr-2014
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1493902237
  • ISBN-13: 9781493902231
Teised raamatud teemal:

This book discusses a number of challenges faced by designers of wireless receivers, given complications caused by the shrinking of electronic and mobile devices circuitry into ever-smaller sizes and the resulting complications on the manufacturability, production yield, and the end price of the products. The authors describe the impact of process technology on the performance of the end product and equip RF designers with countermeasures to cope with such problems. The mechanisms by which these problems arise are analyzed in detail and novel solutions are provided, including design guidelines for receivers with robustness to process variations and details of circuit blocks that obtain the required performance level.

  • Describes RF receiver frontends and their building blocks from a system- and circuit-level perspective;
  • Provides system-level analysis of a generic RF receiver frontend with robustness to process variations;
  • Includes details of CMOS circuit design at 60GHz and reconfigurable circuits at 60GHz;
  • Covers millimeter-wave circuit design with robustness to process variations.


This book discusses wireless receiver design challenges, given the shrinking of circuitry into ever-smaller sizes and resulting complications on manufacturability, production yield and end price of the products. Includes countermeasures for RF designers.
1 Introduction
1(6)
2 System-Level Design for Robustness
7(32)
2.1 Bit Error Rate, Noise, Gain, and Nonlinearity
9(2)
2.2 Performance Requirements
11(2)
2.3 Block-Level Impact
13(5)
2.3.1 General Case
13(4)
2.3.2 Special Case: Zero-IF Receiver and Worst-Case Nonlinearity
17(1)
2.4 Sensitivity to Block-Level Performance
18(5)
2.4.1 General Case
18(3)
2.4.2 Special Case: Zero-IF Receiver and Worst-Case Nonlinearity
21(2)
2.5 Design for Robustness
23(6)
2.5.1 Constant-Sensitivity Approach
24(1)
2.5.2 Reduced-Second-Order-Sensitivity Approach
25(1)
2.5.3 Optimum-Power Design
26(2)
2.5.4 Summary and Discussion
28(1)
2.6 Case Study
29(9)
2.6.1 Receiver Without ADC
29(5)
2.6.2 Receiver with ADC
34(4)
2.7 Conclusions
38(1)
3 Layout and Measurements at 60 GHz
39(22)
3.1 Layout Challenges
39(10)
3.1.1 Impact of Parasitics
40(2)
3.1.2 Electromagnetic Simulation of Complex Structures
42(2)
3.1.3 Substrate Losses
44(3)
3.1.4 Cross-Talk Shielding and Grounding
47(2)
3.2 Measurement Setup
49(9)
3.2.1 Calibration and s-Parameter Measurement
52(1)
3.2.2 Noise Measurement
53(4)
3.2.3 Nonlinearity Measurement
57(1)
3.2.4 Phase Noise Measurement
58(1)
3.3 Conclusions
58(3)
4 Component Design at 60 GHz
61(64)
4.1 Low Noise Amplifier
61(14)
4.1.1 Topology Selection
61(2)
4.1.2 Stability and Noise Analysis
63(6)
4.1.3 Circuit Design
69(3)
4.1.4 Measurement Results
72(3)
4.2 Mixer
75(24)
4.2.1 Topology Selection
75(2)
4.2.2 Gain and Noise Analysis
77(10)
4.2.3 Third Order Nonlinearity Analysis
87(7)
4.2.4 Second Order Nonlinearity Analysis
94(3)
4.2.5 Circuit Design and Layout
97(1)
4.2.6 Measurement Results
98(1)
4.3 Quadrature VCO
99(16)
4.3.1 Quadrature Signal Generation Techniques
100(3)
4.3.2 Tuning Range
103(4)
4.3.3 Phase Noise
107(2)
4.3.4 Circuit Design and Layout
109(1)
4.3.5 Measurement and Simulation Results
110(5)
4.4 Miller-Effect-Based VCO
115(6)
4.4.1 Tuning Using Miller Effect
117(1)
4.4.2 Design
118(3)
4.5 Measurement and Simulation Results
121(2)
4.6 Conclusions
123(2)
5 Smart-Component Design at 60 GHz
125(36)
5.1 Wideband IP2 Correction
126(24)
5.1.1 IMD2 Cancellation Methods
128(3)
5.1.2 3D Tuning for Wideband IMD2 Cancellation
131(1)
5.1.3 Circuit Design and Layout
131(3)
5.1.4 Tuning Algorithms
134(3)
5.1.5 Measurement Results
137(11)
5.1.6 Discussion
148(2)
5.2 Adjustment of Process Variation Impact
150(9)
5.2.1 Tunability in Different LNA Topologies
150(2)
5.2.2 Tunability in Other Stages
152(1)
5.2.3 Overall Design Considerations
152(4)
5.2.4 Correcting the Corner Performance
156(2)
5.2.5 Layout Impact Approximated
158(1)
5.3 Conclusions
159(2)
6 Conclusions and Recommendations
161(4)
6.1 Conclusions
161(1)
6.2 Recommendations
162(3)
Appendix A Optimizing Total Power Consumption by Defining Total Noise and Total Nonlinearity 165(2)
Glossary 167(6)
Bibliography 173