List of Contributors |
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xv | |
Biography |
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xix | |
Acknowledgment |
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xxi | |
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1 | (16) |
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1.1 What Are the Key PA Performance Metrics? |
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2 | (4) |
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3 | (1) |
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1.1.2 PA Power Efficiency |
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3 | (1) |
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4 | (1) |
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1.1.4 PA Robustness to Antenna Load Variations |
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5 | (1) |
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1.2 Unique Advantages of Silicon-Based PAs |
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6 | (2) |
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1.3 Silicon-Based mm-Wave and THz Signal Generation—A New Frontier |
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8 | (3) |
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11 | (6) |
Part I Power Amplifier Design Methodologies |
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Chapter 2 Power amplifier fundamentals |
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17 | (44) |
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2.1 Power Generation and Power Matching |
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18 | (5) |
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2.1.1 I-V Curve and Power Generation Capability |
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18 | (2) |
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2.1.2 Power Gain and Efficiency |
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20 | (1) |
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21 | (2) |
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2.2 Classical Linear Power Amplifiers: Classes A, AB, B, and C |
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23 | (5) |
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2.2.1 Class-A Power Amplifier |
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25 | (1) |
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2.2.2 Class-B Power Amplifier |
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25 | (1) |
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2.2.3 Class-AB Power Amplifier |
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26 | (1) |
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2.2.4 Class C Power Amplifier |
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27 | (1) |
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2.3 Linear Power Amplifier |
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28 | (13) |
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2.3.1 Analysis of Device Linearity Characteristics |
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28 | (7) |
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2.3.2 Evaluation of Power Amplifier Linearity |
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35 | (3) |
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2.3.3 Realization of the Optimized Linear CMOS PA |
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38 | (3) |
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2.4 Switching Power Amplifier |
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41 | (7) |
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2.4.1 Class F and Class F-1 Amplifier |
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41 | (2) |
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2.4.2 Class D and Class D-1 Amplifiers |
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43 | (2) |
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2.4.3 Class AB/F Amplifier |
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45 | (3) |
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48 | (10) |
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2.5.1 Ideal Design Formula of Class E Amplifier |
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49 | (3) |
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2.5.2 Real Operation of Class-E Amplifier |
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52 | (3) |
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2.5.3 Operation of the Class E PA Beyond Maximum Operation Frequency |
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55 | (3) |
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58 | (1) |
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58 | (3) |
Part II RF Power Amplifier Design Examples |
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Chapter 3 CMOS power amplifier design for wireless connectivity applications: a highly linear WLAN power amplifier in advanced SoC CMOS |
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61 | (28) |
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61 | (3) |
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3.2 Design Considerations of Class-AB PA for WLAN |
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64 | (2) |
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3.3 Circuit Architecture and Layout Structure |
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66 | (2) |
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3.4 Shielded Concentric Transformers |
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68 | (2) |
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3.5 Circuit Implementations |
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70 | (3) |
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3.6 Measured Results of Experimental Design in Low-Resistivity Wafer |
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73 | (3) |
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3.7 Improved Design and Measurement Results in Regular Wafer |
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76 | (2) |
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3.8 PA Integration for SoC |
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78 | (4) |
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3.9 Performance Summaries and Comparison of State of the Art |
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82 | (4) |
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86 | (1) |
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86 | (1) |
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87 | (2) |
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Chapter 4 CMOS power amplifier design for cellular applications: an EDGE/GSM dual-mode quad-band PA in 0.18µm CMOS |
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89 | (22) |
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89 | (3) |
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4.2 Standards for Cellular RF Systems |
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92 | (4) |
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96 | (3) |
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4.4 Linearization for Nonlinear Cgd |
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99 | (4) |
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103 | (1) |
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103 | (5) |
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108 | (1) |
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109 | (2) |
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Chapter 5 Energy-efficiency enhancement and linear amplifications: a transformer-based Doherty approach |
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111 | (24) |
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111 | (3) |
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5.2 Optimization of SCT Transformer-Based Doherty Power Amplifiers |
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114 | (9) |
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5.2.1 Optimization of 1:1 Transformers |
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114 | (2) |
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5.2.2 Optimization of Series-Combining Transformers SCT) for Doherty Operation |
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116 | (7) |
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5.3 Implementation of SCT Transformer-Based Doherty Power Amplifier for WLAN Applications |
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123 | (3) |
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126 | (5) |
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131 | (1) |
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131 | (4) |
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Chapter 6 Linear power amplification with high back-off efficiency: an out-phasing approach |
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135 | (48) |
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136 | (1) |
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6.2 System Impact from Impairments of Outphasing Design |
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137 | (6) |
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6.3 Outphasing Topologies |
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143 | (6) |
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6.3.1 Topology Selection of Active Devices |
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143 | (3) |
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6.3.2 Power Combiner for Outphasing |
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146 | (3) |
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6.4 Linearity Analysis of Outphasing System Using Class-D and Class-F PA |
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149 | (5) |
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6.5 Back-Off Efficiency Enhancement in Outphasing |
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154 | (9) |
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6.5.1 Transformer Connection Arrangement Optimization |
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154 | (2) |
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6.5.2 Dynamic Power Control with a Multisection Transformer Combiner |
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156 | (7) |
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6.6 Implementation Examples and Considerations |
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163 | (16) |
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6.6.1 Design Example I: 45-nm Outphasing PA with Lumped Based on λ/4 Power Combiner |
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164 | (4) |
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6.6.2 Design Example II: 32-nm Outphasing PA with 2:1 Transformer Combiner |
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168 | (3) |
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6.6.3 Design Example III: 45-nm Outphasing PA with Dynamic Power Control |
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171 | (7) |
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6.6.4 Design Example V: Consideration of PA Integration in Transmitter |
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178 | (1) |
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179 | (1) |
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179 | (4) |
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Chapter 7 Energy efficiency enhancement and linear amplifications: an envelope-tracking (ET) approach |
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183 | (28) |
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183 | (5) |
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7.2 Pseudo-Differential SiGe PA Design |
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188 | (2) |
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7.3 Envelope-Shaping Analysis for the ET-PA System |
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190 | (8) |
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7.3.1 Discrete EM for ET-PA System Analysis |
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190 | (1) |
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7.3.2 Envelope-Shaping Method Investigation: DC Shifting with Envelope Scaling |
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191 | (4) |
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7.3.3 Additional Envelope-Shaping Method Investigation: Envelope Clipping |
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195 | (3) |
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7.4 Integrated CMOS EM IC Design |
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198 | (3) |
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7.5 ET-PA Measurement Results with the EM IC |
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201 | (6) |
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207 | (1) |
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207 | (1) |
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208 | (3) |
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Chapter 8 A digital RF power amplification technique based on the switched-capacitor circuit |
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211 | (36) |
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212 | (1) |
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8.2 Polar and Digital Power Amplifiers |
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213 | (2) |
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213 | (1) |
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214 | (1) |
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215 | (10) |
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8.3.1 Ideal Operation of the SCPA |
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215 | (2) |
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8.3.2 Output Power and Efficiency of the SCPA |
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217 | (4) |
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8.3.3 AM—PM and AM—AM Distortion |
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221 | (4) |
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8.4 SCPA Prototype Implementation and Experimental Results |
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225 | (6) |
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8.4.1 Prototype Implementation |
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225 | (2) |
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8.4.2 Experimental Results |
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227 | (4) |
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8.5 Extended SCPA Architectures |
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231 | (12) |
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8.5.1 Class-G SCPA for Improved Efficiency |
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231 | (10) |
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8.5.2 Power-Combined SCPA for Higher Output Power |
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241 | (2) |
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243 | (2) |
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245 | (2) |
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Chapter 9 A transformer-based reconfigurable digital polar Doherty power amplifier fully integrated in bulk CMOS |
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247 | (30) |
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247 | (2) |
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9.2 Digital Polar Doherty PA Architecture |
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249 | (4) |
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9.2.1 Doherty Operating Principle Review |
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249 | (2) |
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9.2.2 Digital Polar Doherty Architecture |
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251 | (1) |
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9.2.3 PA Core and Driver Design |
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252 | (1) |
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9.3 Passive Network Designs in the Fully Integrated Doherty PA |
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253 | (9) |
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9.3.1 Doherty Input Passive Network Design |
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253 | (1) |
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9.3.2 Doherty Output Passive Network Design |
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253 | (9) |
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262 | (9) |
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9.4.1 Continuous Wave Measurement |
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263 | (2) |
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9.4.2 Modulated Signal Measurement |
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265 | (6) |
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271 | (1) |
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271 | (6) |
Part III mm-Wave And Terahertz Power Generation Design Examples |
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Chapter 10 60 GHz all silicon radio IC: how it all started |
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277 | (36) |
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278 | (5) |
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10.2 Power Amplifier Design |
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283 | (15) |
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10.2.1 Design Techniques, Characterization and Measurement Procedures |
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283 | (3) |
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10.2.2 Three-Stage Power Amplifier |
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286 | (5) |
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10.2.3 Four-Stage Power Amplifier |
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291 | (5) |
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10.2.4 Modified Four-Stage Power Amplifier |
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296 | (2) |
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10.3 Power Amplifier Integration into a Single-Chip Radio Transceiver |
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298 | (11) |
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10.3.1 Transmitter Architecture |
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298 | (1) |
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299 | (1) |
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10.3.3 Dual-Gate Up-Conversion Mixer |
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300 | (1) |
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10.3.4 Power Amplifier Integrated with Up-Converter and Temperature Sensor |
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301 | (2) |
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10.3.5 Integrated Transmitter Front-End into a Single-Chip Radio Transceiver |
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303 | (6) |
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309 | (1) |
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309 | (4) |
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Chapter 11 mm-Wave power-combining architectures: current combining |
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313 | (22) |
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313 | (2) |
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11.2 Two-Way Current-Combining PA |
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315 | (12) |
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11.2.1 mm-Wave CMOS PA Challenges |
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315 | (1) |
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11.2.2 Power Combiner Comparisons |
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316 | (1) |
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11.2.3 Two-Way Transformer-Based Current Combiner |
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317 | (6) |
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323 | (4) |
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327 | (3) |
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330 | (1) |
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331 | (1) |
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331 | (4) |
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Chapter 12 mm-Wave power-combining architectures: hybrid combining |
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335 | (26) |
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12.1 Why Millimeter Wave, and Why Silicon |
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335 | (1) |
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12.2 Power-Combining Techniques |
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336 | (5) |
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12.2.1 Spatial Power Combination |
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337 | (2) |
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12.2.2 Monolithic On-Chip Power Combination |
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339 | (2) |
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12.3 Design of CMOS Transformer-Based Power-Combining PA |
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341 | (13) |
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12.3.1 Issues of Transformer-Based Power Combiner |
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342 | (3) |
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12.3.2 The Effect of Transformer Design on Power Combiner |
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345 | (2) |
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12.3.3 Proposed Architectures for Fully Coherent Power Combiner |
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347 | (4) |
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12.3.4 Design of the Fully Synchronous Transformer-Based Power Combining Amplifier |
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351 | (3) |
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12.4 Experimental Results |
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354 | (2) |
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356 | (1) |
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357 | (1) |
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357 | (4) |
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Chapter 13 mm-Wave CMOS design above 60 GHz |
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361 | (20) |
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361 | (1) |
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13.2 NMOS Device performance at mm-Wave Frequencies |
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362 | (6) |
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13.2.1 Power Gain at mm-Wave Frequencies |
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363 | (1) |
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13.2.2 Device Stabilization |
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364 | (4) |
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368 | (5) |
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13.3.1 Conjugate Matching |
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368 | (1) |
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13.3.2 Disadvantages of Conjugate Matching |
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368 | (2) |
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13.3.3 Differential Matching Circuits |
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370 | (3) |
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13.4 mm-Wave Integrated Circuits |
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373 | (7) |
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13.4.1 100-GHz Differential Amplifier in 90-nm CMOS |
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374 | (1) |
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13.4.2 94-GHz Differential PA in 45-nm LP CMOS |
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374 | (3) |
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13.4.3 120-GHz 10-Gb/s CMOS Transmitter |
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377 | (3) |
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380 | (1) |
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Chapter 14 Self-healing techniques for robust mm-Wave power amplification |
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381 | (28) |
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381 | (3) |
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14.2 Power Amplification with Reconfigurability |
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384 | (1) |
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14.3 mm-Wave Power Amplification with Self-healing Capability |
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385 | (14) |
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14.3.1 mm-Wave CMOS Power Amplification Design Challenges and Brief Review |
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385 | (1) |
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14.3.2 Proposed mm-Wave CMOS Power Amplifier and Control Knobs Design |
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386 | (8) |
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14.3.3 Self-Healing Techniques and Algorithm |
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394 | (5) |
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399 | (7) |
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406 | (1) |
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406 | (1) |
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406 | (3) |
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Chapter 15 mm-Wave class-E PA design in CMOS |
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409 | (26) |
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409 | (2) |
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15.2 Design Background: Theory of Operation and Starting Design Equations |
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411 | (2) |
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15.3 Circuit Implementation in 32-nm SOI CMOS |
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413 | (10) |
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15.3.1 Core PA Device Size Determination |
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414 | (1) |
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15.3.2 Input Matching Network Design |
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415 | (2) |
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417 | (1) |
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15.3.4 Output Network Design |
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418 | (2) |
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15.3.5 FET Layout Methodology |
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420 | (1) |
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15.3.6 Simulation Results |
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421 | (2) |
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15.4 Measurement and Results |
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423 | (8) |
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423 | (3) |
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15.4.2 Measurement Results |
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426 | (4) |
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430 | (1) |
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431 | (1) |
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431 | (4) |
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Chapter 16 High-speed, efficient, millimeter-wave power-mixer-based digital transmitters |
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435 | (26) |
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435 | (2) |
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437 | (2) |
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16.3 Design and Implementation |
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439 | (7) |
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16.3.1 Segmented Power Stage |
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439 | (2) |
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441 | (2) |
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16.3.3 Input Distribution and Drivers |
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443 | (3) |
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16.4 Chip Implementation and Measurement Results |
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446 | (12) |
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16.4.1 Continuous Wave Measurements |
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448 | (2) |
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16.4.2 Modulation Measurements |
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450 | (4) |
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16.4.3 EVM Contribution Due to Measurement Setup and Calibration |
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454 | (3) |
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16.4.4 Segment Reliability Under Stress |
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457 | (1) |
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458 | (2) |
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460 | (1) |
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Chapter 17 THz power generation beyond transistor fmax |
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461 | (24) |
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17.1 Multiple-Push Oscillators |
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463 | (2) |
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17.2 Sub-terahertz CMOS Push-Push Oscillator |
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465 | (10) |
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17.2.1 Design Considerations |
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465 | (5) |
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17.2.2 Quasi-optical Measurement |
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470 | (3) |
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17.2.3 Experimental Results |
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473 | (2) |
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17.3 Quadruple-Push Oscillator in CMOS |
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475 | (7) |
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17.3.1 Design Considerations |
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476 | (4) |
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17.3.2 Measurement Results |
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480 | (2) |
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482 | (1) |
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483 | (2) |
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Chapter 18 THz signal generation, radiation, and beam-forming in silicon: a circuit and electromagnetics co-design approach |
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485 | (34) |
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486 | (1) |
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18.2 Current THz Technology |
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487 | (1) |
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18.3 Power Generation Above fmax |
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488 | (2) |
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18.4 Inverse Design Approach: Design Evolution of Distributed Active Radiator (DAR) |
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490 | (4) |
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18.4.1 Conceptual Synthesis of Fundamental and Harmonic Surface Currents in Silicon |
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490 | (1) |
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18.4.2 Active Synthesis of Currents for the Desired Harmonic Radiation |
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491 | (2) |
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18.4.3 Distributed Active Radiation: Complete Chain of DC-Radiated THz Conversion |
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493 | (1) |
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18.5 Design and optimization of DAR |
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494 | (7) |
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18.5.1 Fundamental Frequency of Oscillation |
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494 | (2) |
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18.5.2 Ground Plane Aperture and Optimum Impedance Matching |
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496 | (1) |
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18.5.3 Radiation Properties, Bandwidth, and Comparison with Classical Antennas |
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497 | (3) |
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18.5.4 Bias Network Design |
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500 | (1) |
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18.6 Distributed Active Radiator Beam-Scanning Architecture at 0.28 THz |
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501 | (2) |
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18.7 Transmitter circuit blocks |
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503 | (3) |
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18.7.1 94-GHz Voltage-Controlled Oscillator and Buffers |
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503 | (1) |
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18.7.2 47-GHz Injection Locked Divide-by-Two |
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504 | (1) |
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18.7.3 47-GHz Phase Rotator |
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504 | (2) |
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18.7.4 141-GHz Injection-Locked Frequency Tripler |
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506 | (1) |
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506 | (8) |
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18.8.1 Central VCO and the Buffers |
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508 | (1) |
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18.8.2 Quadrature Signal Generation and Phase Rotation |
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508 | (2) |
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510 | (4) |
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514 | (1) |
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515 | (4) |
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Chapter 19 Silicon-based THz signal generation with multiphase subharmonic injection-locking oscillators |
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519 | (28) |
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519 | (3) |
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19.2 Multiphase IL technique |
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522 | (6) |
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19.2.1 N-Push (Multiphase) LC Ring Oscillator |
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522 | (2) |
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19.2.2 Multiphase IL Scheme versus Single-Phase IL Scheme |
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524 | (4) |
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19.3 A Scalable and Cascadable Active Frequency Multiplier Architecture for THz Signal Generation |
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528 | (2) |
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19.4 Design of Silicon-Based 500-GHz Signal Generation System |
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530 | (9) |
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19.4.1 The Three-Phase 168-GHz Oscillator (Innermost Ring ILO) |
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530 | (4) |
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19.4.2 The Three-Phase 84-GHz Oscillator (Middle Ring ILO) |
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534 | (3) |
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19.4.3 The Three-Phase 42-GHz Oscillator (Outermost Ring VCO) |
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537 | (2) |
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539 | (5) |
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544 | (1) |
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544 | (3) |
Index |
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547 | |