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Robust Sigma Delta Converters: And Their Application in Low-Power Highly-Digitized Flexible Receivers 2011 ed. [Kõva köide]

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  • Formaat: Hardback, 296 pages, kõrgus x laius: 235x155 mm, kaal: 1380 g, XXIV, 296 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 09-Feb-2011
  • Kirjastus: Springer
  • ISBN-10: 940070643X
  • ISBN-13: 9789400706439
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Robust Sigma Delta Converters: And Their Application in Low-Power Highly-Digitized Flexible Receivers 2011 ed.Suurem pilt
  • Formaat: Hardback, 296 pages, kõrgus x laius: 235x155 mm, kaal: 1380 g, XXIV, 296 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 09-Feb-2011
  • Kirjastus: Springer
  • ISBN-10: 940070643X
  • ISBN-13: 9789400706439
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9789400706439.html
Märksõnad:
Robust Sigma-Delta Converters studies how to deal with the ever increasing requirements on IP, and how the technological advances can be exploited with the right design methodology. The book's main objective is to explore implementation possibilities of high quality Sigma-Delta modulators.

Sigma Delta converters are a very popular choice for the A/D converter in multi-standard, mobile and cellular receivers. Key A/D converter specifications are high dynamic range, robustness, scalability, low-power and low EMI. Robust Sigma Delta Converters presents a requirement derivation of a Sigma Delta modulator applied in a receiver for cellular and connectivity, and shows trade-offs between RF and ADC. The book proposes to categorize these requirements in 5 quality indicators which can be used to qualify a system, namely accuracy, robustness, flexibility, efficiency and emission. In the book these quality indicators are used to categorize Sigma Delta converter theory. A few highlights on each of these quality indicators are;Quality indicators: provide a means to quantify system quality.Accuracy: introduction of new Sigma Delta Modulator architectures.Robustness: a significant extension on clock jitter theory based on phase and error amplitude error models. Extension of the theory describing aliasing in Sigma Delta converters for different types of DACs in the feedback loop. Flexibility: introduction of a Sigma Delta converter bandwidth scaling theory leading to very flexible Sigma Delta converters. Efficiency: introduction of new Figure-of-Merits which better reflect performance-power trade-offs. Emission: analysis of Sigma Delta modulators on emission is not part of the bookThe quality indicators also reveal that, to exploit nowadays advanced IC technologies, things should be done as much as possible digital up to a limit where system optimization allows reducing system margins. At the end of the book Sigma Delta converter implementations are shown which are digitized on application-, architecture-, circuit- and layout-level.Robust Sigma Delta Converters is written under the assumption that the reader has some background in receivers and in A/D conversion.
1 Introduction 1(12)
1.1 Advanced, Multi-standard Cellular and Connectivity Terminals for the Mass Market
2(8)
1.1.1 Complexity: Mobile Phone Trends, Its Impact on the Transceiver and the Quest for Integration
3(4)
1.1.2 Transistor Scaling: VLSI and Moore
7(2)
1.1.3 Smarter Circuits: ΣΔ Modulators for Mobile Applications
9(1)
1.2 Book Aims
10(1)
1.3 Book Scope
11(1)
1.4 Outline
11(2)
2 System Quality Indicators 13(14)
2.1 The System Function and Its In- and Outputs
14(1)
2.2 System Quality
15(3)
2.2.1 Accuracy
16(1)
2.2.2 Robustness to Secondary Inputs
16(1)
2.2.3 Flexibility
16(1)
2.2.4 Efficiency
17(1)
2.2.5 Emission of Secondary Outputs
17(1)
2.3 The Digital Revolution
18(5)
2.3.1 The Analog-Digital Interface
19(1)
2.3.2 Digital Systems and the Quality Indicators
20(3)
2.4 Conclusions
23(4)
3 Integrated Receiver Architectures for Cellular and Connectivity 27(6)
3.1 Wireless Receiver Architectures for Digital Communication
27(3)
3.2 Receiver Architecture and the Quality Indicators
30(1)
3.3 Conclusions
31(2)
4 Specifications for A/D Converters in Cellular and Connectivity Receivers 33(38)
4.1 IF Choice
34(11)
4.1.1 Image Rejection
34(1)
4.1.2 Zero IF Architecture
35(2)
4.1.3 Near Zero and High IF Architecture
37(1)
4.1.4 IF Assessment
38(1)
4.1.5 DC Offset and Noise
38(3)
4.1.6 RF Front-End and ADC 1/f-Thermal Noise Corner Frequency
41(4)
4.2 Top-End of the ADC DR
45(4)
4.2.1 Signal Levels, Selectivity, and Maximum ADC Input Signal
46(2)
4.2.2 Crest Factor
48(1)
4.3 Receiver Gain
49(1)
4.3.1 Narrow vs. Broad Band AGC
50(1)
4.4 Bottom-End of the ADC DR
50(3)
4.4.1 Receiver SNR Requirement
50(1)
4.4.2 Receiver Noise Figure and ADC Noise Floor
51(2)
4.5 DR of the ADC
53(1)
4.5.1 DR of a Quadrature ADC
53(1)
4.6 RF Front-End and ADC Linearity Requirements
54(7)
4.6.1 Second and Third Order Harmonic Distortion
54(1)
4.6.2 Second and Third Order Intermodulation and IP2 and IP3
55(3)
4.6.3 Third Order Cross-Modulation
58(1)
4.6.4 Distortion in a Quadrature ADC
59(2)
4.7 Example Receiver Partitioning: Receiver for a GSM Mobile Phone
61(6)
4.7.1 IF Choice and Image Rejection
62(1)
4.7.2 Top-End of the ADC Dynamic Range
63(2)
4.7.3 Receiver Sensitivity Requirement and the Bottom-End of the ADC Dynamic Range
65(1)
4.7.4 Receiver Linearity Requirement and ADC Linearity
66(1)
4.8 ADC Requirements, the System Quality Indicators and ΣΔ Modulators as the ADC Architecture
67(3)
4.9 Conclusions
70(1)
5 ΣΔ Modulator Algorithmic Accuracy 71(20)
5.1 ΣΔ Modulators with 1-bit Quantizer and 1-bit DAC
73(5)
5.2 ΣΔ Modulators with b-bit Quantizer and b-bit DAC
78(1)
5.3 ΣΔ Modulators with 1.5-bit Quantizer and DAC
79(1)
5.4 ΣΔ Modulators with Multiple Quantizers and 1-bit DAC
80(2)
5.5 ΣΔ Modulators with Additive Error-Feedback Loops
82(5)
5.6 Cascaded ΣΔ Modulators
87(1)
5.7 Conclusions
88(3)
6 ΣΔ Modulator Robustness 91(84)
6.1 Portable, Technology Robust Analog IP and Time-to-Market
92(5)
6.1.1 Technology Scaling and Its Impact on Analog Design Parameters
93(1)
6.1.2 A Design Methodology to Increase the Portability of Analog IP
94(3)
6.2 Continuous Time vs. Discrete Time Loop Filter
97(2)
6.3 Feed-Forward vs. Feedback Loop Filter
99(2)
6.4 Gain Accuracy
101(4)
6.4.1 ΣΔ Modulator with 1-bit Quantizer and 1-bit DAC
101(1)
6.4.2 ΣΔ Modulator with b-bit Quantizer and b-bit DAC
101(1)
6.4.3 ΣΔ Modulator with Multiple Quantizers and 1-bit DAC
101(1)
6.4.4 ΣΔ Modulator with Additive Error Feedback Loops
102(2)
6.4.5 Cascaded ΣΔ Modulators
104(1)
6.5 Circuit Noise of the Modulator's Input Stage and DAC
105(3)
6.5.1 RC Integrator Input Stage and SI Feedback DAC
105(1)
6.5.2 RC Integrator Input Stage and SR Feedback DAC
106(1)
6.5.3 RC Integrator Input Stage and SC Feedback DAC
106(1)
6.5.4 Impact of Supply Voltage on the Circuit Noise Requirements
107(1)
6.6 Non-linearity
108(8)
6.6.1 Non-linearity in the Input Stage
108(3)
6.6.2 Non-linearity in the Quantizer Decision Levels
111(1)
6.6.3 Inter-Symbol-Interference in the Feedback DAC
112(1)
6.6.4 Non-linearity in the Output Levels of the Feedback DAC
113(3)
6.7 Aliasing in ΣΔ Modulators
116(11)
6.7.1 Aliasing in the Quantizer
116(1)
6.7.2 ΣΔ Modulator with an SI Feedback DAC
117(3)
6.7.3 ΣΔ Modulator with an SR Feedback DAC
120(2)
6.7.4 ΣΔ Modulator with an SC Feedback DAC
122(5)
6.8 Excess Loop Delay
127(5)
6.8.1 Excess Time Delay Compensation
128(1)
6.8.2 Excess Phase Compensation
129(2)
6.8.3 DAC Feedback Pulse Shape and Delay
131(1)
6.9 Clock Jitter in CT ΣΔ Modulators
132(37)
6.9.1 The TAJE Model
133(6)
6.9.2 The TPJE Model: Sine Wave Induced Jitter
139(12)
6.9.3 The TPJE Model: Substitution of White Noise Jitter in the Sine Wave Induced Jitter Model
151(10)
6.9.4 The TPJE Model: SI Versus SC Feedback DAC
161(1)
6.9.5 The TPJE Model: An Application Driven Choice Between SI Versus SC Feedback DAC
162(7)
6.10 Conclusions
169(6)
7 ΣΔ Modulator Flexibility 175(14)
7.1 Receiver Dictated Flexibility Requirements
175(2)
7.2 ΣΔ Modulator Clock Flexibility
177(6)
7.2.1 Receiver Architecture with LO-Dependent ADC Clock
178(1)
7.2.2 Receiver Architecture with a Flexible and Independent Clock for the ADC
179(1)
7.2.3 Receiver Architecture with Fixed, Independent ADC Clock
180(2)
7.2.4 Choice of Clock Strategy
182(1)
7.3 Input Stage and DAC Flexibility
183(1)
7.4 Loop-Filter Flexibility
183(2)
7.5 Quantizer Flexibility
185(1)
7.6 Conclusions
186(3)
8 ΣΔ Modulator Efficiency 189(24)
8.1 Power Efficiency FOM: FOMDR
191(3)
8.1.1 Benchmarking with FOMDR
193(1)
8.2 Power Efficiency FOM: FOMeq,th
194(6)
8.2.1 Benchmarking with FOMeq,th
197(3)
8.3 Distortion FOM: FOMHD3D
200(5)
8.3.1 Benchmarking with FOMHD3D
202(3)
8.4 Area FOM: FOMarea
205(6)
8.4.1 Benchmarking with FOMarea
209(2)
8.5 Conclusions
211(2)
9 ΣΔ Modulator Implementations and the Quality Indicators 213(50)
9.1 Digitization at System/Application Level: ΣΔ Modulators for Highly Digitized Receivers
214(26)
9.1.1 A 1.5-bit ΣΔ Modulator for UMTS
215(7)
9.1.2 A Triple-Mode ΣΔ Modulator for GSM-EDGE, CDMA2000 and UMTS
222(10)
9.1.3 An Extremely Scalable ΣΔ Modulator for Cellular and Wireless Applications
232(6)
9.1.4 Multi-mode Modulator Clock Strategy
238(2)
9.2 Digitization at Analog IP Architecture Level: A Hybrid, Inverter-Based ΣΔ Modulator
240(9)
9.2.1 ΣΔ Modulator Architecture
241(1)
9.2.2 Circuit Design
242(3)
9.2.3 Experimental Results
245(3)
9.2.4 Conclusions
248(1)
9.3 Digitization at Circuit and Layout Level: Technology Portable ΣΔ Modulators
249(8)
9.3.1 ΣΔ Modulator Architecure
250(1)
9.3.2 Circuit Design and Layout
251(5)
9.3.3 Conclusions
256(1)
9.4 Implementations Judged on the FOMs and Quality Indicators
257(3)
9.5 Conclusions
260(3)
10 Conclusions 263(2)
A Harmonic and Intermodulation Distortion in an I&Q System 265(4)
A.1 Double Sided Spectrum of Second and Third Order Distortion of a Complex Signal
265(1)
A.2 Double Sided Spectrum of Second and Third Order Distortion in a Complex System
266(3)
B Distortion of a Differential Input Transistor Pair Biased in Weak Inversion 269(2)
C Fourier Series Expansion and Return-to-Zero 271(2)
D Clock Jitter in an I&Q System According to the TPJE Clock Jitter Model 273(2)
References 275(14)
Index 289
Robert H.M. van Veldhoven was born in Eindhoven, The Netherlands, in 1972. After finishing his pre-education (HAVO) at ''Het Hertog-Jan College'' in Valkenswaard, he started to study ''hands-on'' electronics at the MTS ''Leonardo Da Vinci college'' in Eindhoven. After 2 years at the MTS, he started studying electrical engineering at the polytechnical college ''Fontys Hogescholen'' in Eindhoven. In 1996 he joined the Mixed-Signal Circuits and Systems group at Philips Research after successfully finishing his graduation project on a low-power Sigma Delta modulator for multi-meter applications. After working 3 years at Philips he started to pursue a master degree in Electronics from the Technical University of Eindhoven, which he successfully finished in 2003. After working for 10 years at Philips Research, he joined the Mixed-Signal Circuits and Systems group at NXP Semiconductor Research in Eindhoven in 2006, where he is an expert in the field of high-resolution A/D and D/A converters, and integrated circuits for instrumentation-, sensor-, audio-, and radio-systems. In 2010 he pursued a PhD degree in Electronic Engineering. Van Veldhoven holds various US patents and published various papers at leading conferences and in leading journals, and is reviewer for several professional journals and conferences. In 2004 and 2010, he was invited to give a forum presentation at the ISSCC about \sd modulators for wireless and cellular receivers.

Arthur H.M. van Roermund (SM95) was born in Delft, The Netherlands in 1951. He received the M.Sc. degree in electrical engineering in 1975 from the Delft Universi­ty of Technol­ogy and the Ph.D. degree in Applied Sciences from the K.U.Leuven, Belgium, in 1987. From 1975 to 1992 he was with Philips Re­search Laborato­ries in Eindhoven. From 1992 to 1999 he has been a full pro­fessor at the Electrical Engineer­ing Depart­ment of Delft Universi­ty of Technol­ogy, where he was chairman of the Elec­tronics Research Group and member of the management team of DIMES. From 1992 to 1999 he has been chairman of a two-years post-graduate school for chartered designer. From 1992 to 1997 he has been consultant for Philips. October 1999 he joined Eindhoven University of Technology as a full professor, chairing the Mixed-signal Microelectronics Group. Since September 2002 he is also director of research of the Department of Electrical Engineering. He is chairman of the board of ProRISC, a nation-wide microelectronics platform; a member of the ICT research platform for the Netherlands (IPN); and a member of the supervisory board of the NRC Photonics research centre. Since 2001, he is one of the three organisers of the yearly workshop on Advanced Analog Circuit Design (AACD). In 2004 he achieved the Simon Stevin Meester award, coupled to a price of 500.000, for his scientific and technological achievements. In 2007 he was member of an international assessment panel for the Department of Electronics and Information of Politecnico di Milano, and in 2009 for Electronics and Electrical Engineering for the merged Aalto University Finland. He authored/co-authored more than 300 articles and 25 books.