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(MIPS Technologies)
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See MIPS Run 2nd editionSuurem pilt
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Püsilink: https://www.kriso.ee/db/9780120884216.html
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This second edition is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers’ resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux.

Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.

* Completely new material offers the best explanation available on how Linux runs on real hardware.

* Provides a complete, updated and easy-to-use guide to the MIPS instruction set using the MIPS32 standard as the baseline architecture with the MIPS64 as the main option.

* Retains the same engaging writing style that made the first edition so readable, reflecting the authors 20+ years experience in designing systems based on the MIPS architecture.

Arvustused

"This book is a worthwhile read for anyone interested in Linux on MIPS processors or even MIPS and RISC architecture in general." --James Mohr, Linux Magazine, April 2007

Muu info

A complete update to the successful first edition, the most comprehensive and readable book on the MIPs architecture--the engine driving many of today's embedded systems.
Foreword v
Preface xv
Style and Limits xviii
Conventions xviii
Acknowledgments xix
RISCs and MIPS Architectures
1(28)
Pipelines
2(3)
What Makes a Pipeline Inefficient?
3(1)
The Pipeline and Caching
4(1)
The MIPS Five-Stage Pipeline
5(2)
RISC and CISC
7(1)
Great MIPS Chips of the Past and Present
8(15)
R2000 to R3000 Processors
8(1)
The R6000 Processor: A Diversion
9(2)
The First CPU Cores
11(1)
The R4000 Processor: A Revolution
12(1)
The Rise and Fall of the ACE Consortium
12(1)
SGI Acquires MIPS
13(1)
QED: Fast MIPS Processors for Embedded Systems
13(1)
The R10000 Processor and its Successors
14(1)
MIPS Processors in Consumer Electronics
15(1)
MIPS in Network Routers and Laser Printers
15(2)
MIPS Processors in Modern Times
17(3)
The Rebirth of MIPS Technologies
20(1)
The Present Day
21(2)
MIPS Compared with CISC Architectures
23(6)
Constraints on MIPS Instructions
23(1)
Addressing and Memory Accesses
24(1)
Features You Won't Find
25(2)
Programmer-Visible Pipeline Effects
27(2)
MIPS Architecture
29(24)
A Flavor of MIPS Assembly Language
33(1)
Registers
34(4)
Conventional Names and Uses of General-Purpose Registers
35(3)
Integer Multiply Unit and Registers
38(1)
Loading and Storing: Addressing Modes
39(1)
Data Types in Memory and Registers
39(3)
Integer Data Types
39(1)
Unaligned Loads and Stores
40(1)
Floating-Point Data in Memory
41(1)
Synthesized Instructions in Assembly Language
42(1)
MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions
43(4)
To 64 Bits
45(1)
Who Needs 64 Bits?
45(1)
Regarding 64 Bits and No Mode Switch: Data in Registers
46(1)
Basic Address Space
47(3)
Addressing in Simple Systems
49(1)
Kernel versus User Privilege Level
49(1)
The Full Picture: The 64-Bit View of the Memory Map
50(1)
Pipeline Visibility
50(3)
Coprocessor 0: MIPS Processor Control
53(26)
CPU Control Instructions
55(3)
Which Registers Are Relevant When?
58(1)
CPU Control Registers and Their Encoding
59(16)
Status Register (SR)
60(4)
Cause Register
64(1)
Exception Restart Address (EPC) Register
65(2)
Bad Virtual Address (BadVAddr) Register
67(1)
Count/Compare Registers: The On-CPU Timer
68(1)
Processor ID (PRId) Register
68(1)
Config Registers: CPU Resource Information and Configuration
69(4)
EBase and IntCtl: Interrupt and Exception Setup
73(1)
SRSCtl and SRSMap: Shadow Register Setup
74(1)
Load-Linked Address (LLAddr) Register
75(1)
CP0 Hazards---A Trap for the Unwary
75(4)
Hazard Barrier Instructions
76(1)
Instruction Hazards and User Hazards
77(1)
Hazards between CP0 Instructions
77(2)
How Caches Work on MIPS Processors
79(26)
Caches and Cache Management
79(1)
How Caches Work
80(3)
Write-Through Caches in Early MIPS CPUs
83(1)
Write-Back Caches in MIPS CPUs
84(1)
Other Choices in Cache Design
84(2)
Managing Caches
86(2)
L2 and L3 Caches
88(1)
Cache Configurations for MIPS CPUs
88(2)
Programming MIPS32/64 Caches
90(8)
The Cache Instruction
91(1)
Cache Initialization and Tag/Data Registers
92(2)
CacheErr, ERR, and ErrorEPC Registers: Memory/Cache Error Handling
94(1)
Cache Sizing and Figuring Out Configuration
95(1)
Initialization Routines
96(1)
Invalidating or Writing Back a Region of Memory in the Cache
97(1)
Cache Efficiency
98(2)
Reorganizing Software to Influence Cache Efficiency
100(2)
Cache Aliases
102(3)
Exceptions, Interrupts, and Initialization
105(26)
Precise Exceptions
107(2)
Nonprecise Exceptions---The Multiplier in Historic MIPS CPUs
108(1)
When Exceptions Happen
109(1)
Exception Vectors: Where Exception Handling Starts
109(4)
Exception Handling: Basics
113(1)
Returning from an Exception
114(1)
Nesting Exceptions
114(1)
An Exception Routine
115(1)
Interrupts
115(9)
Interrupt Resources in MIPS CPUs
116(2)
Implementing Interrupt Priority in Software
118(2)
Atomicity and Atomic Changes to SR
120(1)
Critical Regions with Interrupts Enabled: Semaphores the MIPS Way
121(2)
Vectored and EIC Interrupts in MIPS32/64 CPUs
123(1)
Shadow Registers
124(1)
Starting Up
124(4)
Probing and Recognizing Your CPU
126(1)
Bootstrap Sequences
127(1)
Starting Up an Application
128(1)
Emulating Instructions
128(3)
Low-level Memory Management and the TLB
131(20)
The TLB/MMU Hardware and What It Does
131(1)
TLB/MMU Registers Described
132(8)
TLB Key Fields---EntryHi and PageMask
134(2)
TLB Output Fields---EntryLo0-1
136(1)
Selecting a TLB Entry---Index, Random, and Wired Registers
137(1)
Page-Table Access Helpers---Context and XContext
138(2)
TLB/MMU Control Instructions
140(1)
Programming the TLB
141(2)
How Refill Happens
142(1)
Using ASIDs
143(1)
The Random Register and Wired Entries
143(1)
Hardware-Friendly Page Tables and Refill Mechanism
143(4)
TLB Miss Handling
145(1)
XTLB Miss Handler
146(1)
Everyday Use of the MIPS TLB
147(2)
Memory Management in a Simpler OS
149(2)
Floating-Point Support
151(32)
A Basic Description of Floating Point
151(1)
The IEEE 754 Standard and Its Background
152(2)
How IEEE Floating-Point Numbers Are Stored
154(4)
IEEE Mantissa and Normalization
155(1)
Reserved Exponent Values for Use with Strange Values
155(1)
MIPS FP Data Formats
156(2)
MIPS Implementation of IEEE 754
158(1)
Need for FP Trap Handler and Emulator in All MIPS CPUs
159(1)
Floating-Point Registers
159(2)
Conventional Names and Uses of Floating-Point Registers
160(1)
Floating-Point Exceptions/Interrupts
161(1)
Floating-Point Control: The Control/Status Register
161(4)
Floating-Point Implementation Register
165(1)
Guide to FP Instructions
166(7)
Load/Store
167(1)
Move between Registers
168(1)
Three-Operand Arithmetic Operations
169(1)
Multiply-Add Operations
170(1)
Unary (Sign-Changing) Operations
170(1)
Conversion Operations
170(1)
Conditional Branch and Test Instructions
171(2)
Paired-Single Floating-Point Instructions and the MIPS-3D ASE
173(6)
Exceptions on Paired-Single Instructions
174(1)
Paired-Single Three-Operand Arithmetic, Multiply-Add, Sign-Changing, and Nonconditional Move Operations
174(1)
Paired-Single Conversion Operations
175(1)
Paired-Single Test and Conditional Move Instructions
176(1)
MIPS-3D Instructions
176(3)
Instruction Timing Requirements
179(1)
Instruction Timing for Speed
179(1)
Initialization and Enabling on Demand
180(1)
Floating-Point Emulation
181(2)
Complete Guide to the MIPS Instruction Set
183(80)
A Simple Example
183(2)
Assembly Instructions and What They Mean
185(25)
U and Non-U Mnemonics
186(1)
Divide Mnemonics
187(1)
Inventory of Instructions
188(22)
Floating-Point Instructions
210(6)
Differences in MIPS32/64 Release 1
216(2)
Regular Instructions Added in Release 2
216(2)
Privileged Instructions Added in Release 2
218(1)
Peculiar Instructions and Their Purposes
218(15)
Load Left/Load Right: Unaligned Load and Store
218(5)
Load-Linked/Store-Conditional
223(1)
Conditional Move Instructions
224(1)
Branch-Likely
225(1)
Integer Multiply-Accumulate and Multiply-Add Instructions
226(1)
Floating-Point Multiply-Add Instructions
227(1)
Multiple FP Condition Bits
228(1)
Prefetch
228(1)
Sync: A Memory Barrier for Loads and Stores
229(2)
Hazard Barrier Instructions
231(1)
Synci: Cache Management for Instruction Writers
232(1)
Read Hardware Register
232(1)
Instruction Encodings
233(19)
Fields in the Instruction Encoding Table
233(18)
Notes on the Instruction Encoding Table
251(1)
Encodings and Simple Implementation
251(1)
Instructions by Functional Group
252(11)
No-op
252(1)
Register/Register Moves
252(1)
Load Constant
253(1)
Arithmetical/Logical
253(2)
Integer Multiply, Divide, and Remainder
255(1)
Integer Multiply-Accumulate
256(1)
Loads and Stores
257(2)
Jumps, Subroutine Calls, and Branches
259(1)
Breakpoint and Trap
260(1)
CP0 Functions
260(1)
Floating Point
261(1)
Limited User-Mode Access to ``Under the Hood'' Features
261(2)
Reading MIPS Assembly Language
263(16)
A Simple Example
264(4)
Syntax Overview
268(1)
Layout, Delimiters, and Identifiers
268(1)
General Rules for Instructions
269(2)
Computational Instructions: Three-, Two-, and One-Register
269(1)
Immediates: Computational Instructions with Constants
270(1)
Regarding 64-Bit and 32-Bit Instructions
271(1)
Addressing Modes
271(3)
Gp-Relative Addressing
273(1)
Object File and Memory Layout
274(5)
Practical Program Layout, Including Stack and Heap
277(2)
Porting Software to the MIPS Architecture
279(32)
Low-Level Software for MIPS Applications: A Checklist of Frequently Encountered Problems
280(1)
Endianness: Words, Bytes, and Bit Order
281(15)
Bits, Bytes, Words, and Integers
281(3)
Software and Endianness
284(3)
Hardware and Endianness
287(6)
Bi-endian Software for a MIPS CPU
293(2)
Portability and Endianness-Independent Code
295(1)
Endianness and Foreign Data
295(1)
Trouble with Visible Caches
296(5)
Cache Management and DMA Data
298(1)
Cache Management and Writing Instructions: Self-Modifying Code
299(1)
Cache Management and Uncached or Write-Through Data
300(1)
Cache Aliases and Page Coloring
301(1)
Memory Access Ordering and Reordering
301(4)
Ordering and Write Buffers
304(1)
Implementing wbflush
304(1)
Writing it in C
305(6)
Wrapping Assembly Code with the GNU C Compiler
305(2)
Memory-Mapped I/O Registers and ``Volatile''
307(1)
Miscellaneous Issues When Writing C for MIPS Applications
308(3)
MIPS Software Standards (ABIs)
311(28)
Data Representations and Alignment
312(7)
Sizes of Basic Types
312(1)
Sizes of ``long'' and Pointer Types
313(1)
Alignment Requirements
313(1)
Memory Layout of Basic Types and How It Changes with Endianness
313(2)
Memory Layout of Structure and Array Types and Alignment
315(1)
Bitfields in Structures
315(3)
Unaligned Data from C
318(1)
Argument Passing and Stack Conventions for MIPS ABIs
319(20)
The Stack, Subroutine Linkage, and Parameter Passing
320(1)
Stack Argument Structure in o32
320(1)
Using Registers to Pass Arguments
321(1)
Examples from the C Library
322(1)
An Exotic Example: Passing Structures
323(1)
Passing a Variable Number of Arguments
324(1)
Returning a Value from a Function
325(1)
Evolving Register-Use Standards: SGIs n32 and n64
326(3)
Stack Layouts, Stack Frames, and Helping Debuggers
329(8)
Variable Number of Arguments and stdargs
337(2)
Debugging MIPS Designs---Debug and Profiling Features
339(24)
The ``EJTAG'' On-chip Debug Unit
341(17)
EJTAG History
343(1)
How the Probe Controls the CPU
343(1)
Debug Communications through JTAG
344(1)
Debug Mode
344(2)
Single-Stepping
346(1)
The dseg Memory Decode Region
346(2)
EJTAG CP0 Registers, Particularly Debug
348(3)
The DCR (Debug Control) Memory-Mapped Register
351(1)
EJTAG Breakpoint Hardware
352(3)
Understanding Breakpoint Conditions
355(1)
Imprecise Debug Breaks
356(1)
PC Sampling with EJTAG
356(1)
Using EJTAG without a Probe
356(2)
Pre-EJTAG Debug Support---Break Instruction and CP0 Watchpoints
358(1)
PDtrace
359(1)
Performance Counters
360(3)
GNU/Linux from Eight Miles High
363(8)
Components
364(4)
Layering in the Kernel
368(3)
MIPS CPU in Exception Mode
368(1)
MIPS CPU with Some or All Interrupts off
369(1)
Interrupt Context
370(1)
Executing the Kernel in Thread Context
370(1)
How Hardware and Software Work Together
371(28)
The Life and Times of an Interrupt
371(4)
High-Performance Interrupt Handling and Linux
374(1)
Threads, Critical Regions, and Atomicity
375(3)
MIPS Architecture and Atomic Operations
376(1)
Linux Spinlocks
377(1)
What Happens on a System Call
378(2)
How Addresses Get Translated in Linux/MIPS Systems
380(19)
What's Memory Translation For?
382(2)
Basic Process Layout and Protection
384(1)
Mapping Process Addresses to Real Memory
385(1)
Paged Mapping Preferred
386(1)
What We Really Want
387(2)
Origins of the MIPS Design
389(3)
Keeping Track of Modified Pages (Simulating ``Dirty'' Bits)
392(1)
How the Kernel Services a TLB Refill Exception
393(4)
Care and Maintenance of the TLB
397(1)
Memory Translation and 64-Bit Pointers
397(2)
MIPS Specific Issues in the Linux Kernel
399(10)
Explicit Cache Management
399(4)
DMA Device Accesses
399(2)
Writing Instructions for Later Execution
401(1)
Cache/Memory Mapping Problems
401(1)
Cache Aliases
402(1)
CP0 Pipeline Hazards
403(1)
Multiprocessor Systems and Coherent Caches
403(3)
Demon Tweaks for a Critical Routine
406(3)
Linux Application Code, PIC, and Libraries
409(6)
How Link Units Get into a Program
411(1)
Global Offset Table (GOT) Organization
412(3)
Appendix A MIPS Multithreading
415(10)
What Is Multithreading?
415(2)
Why Is MT Useful?
417(1)
How to Do Multithreading for MIPS
417(4)
MT in Action
421(4)
Appendix B Other Optional Extensions to the MIPS Instruction Set
425(6)
MIPS16 and MIPS16e ASEs
425(3)
Special Encodings and Instructions in the MIPS16 ASE
426(1)
The MIPS16 ASE Evaluated
427(1)
The MIPS DSP ASE
428(1)
The MDMX ASE
429(2)
MIPS Glossary
431(46)
References
477(4)
Books and Articles
477(1)
Online Resources
478(3)
Index 481


Dominic Sweetman is a member of the last generation of programmers who could reasonably hope to understand computer systems from bottom to top. His rich career began with low-level coding, progressing from OS development to LANs to distributed systems. Dominic is an experienced designer and developer of hardware systems, CPUs, networks, and operating systems. He was a founder member of Whitechapel Workstations, and in 1988 founded Algorithmics, a MIPS consulting firm of which he is the director. Dominic lives with his partner, two grown-up children and three cats in north London.