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Self-Checking and Fault-Tolerant Digital Design [Kõva köide]

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(North Carolina Agricultural and Technical State University)
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Self-Checking and Fault-Tolerant Digital DesignSuurem pilt
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780124343702.html
Märksõnad:
With VLSI chip transistors getting smaller and smaller, today's digital systems are more complex than ever before. This increased complexity leads to more cross-talk, noise, and other sources of transient errors during normal operation. Traditional off-line testing strategies cannot guarantee detection of these transient faults. And with critical applications relying on faster, more powerful chips, fault-tolerant, self-checking mechanisms must be built in to assure reliable operation. Self-Checking and Fault-Tolerant Digital Design deals extensively with self-checking design techniques and is the only book that emphasizes major techniques for hardware fault tolerance. Graduate students in VLSI design courses as well as practicing designers will appreciate this balanced treatment of the concepts and theory underlying fault tolerance along with the practical techniques used to create fault-tolerant systems.

Muu info

* Introduces reliability theory and the importance of maintainability * Presents coding and the construction of several error detecting and correcting codes * Discusses in depth, the available techniques for fail-safe design of combinational circuits * Details checker design techniques for detecting erroneous bits and encoding output of self-checking circuits * Demonstrates how to design self-checking sequential circuits, including a technique for fail-safe state machine design
Preface xi
Fundamentals of Reliability
1(14)
Reliability and the Failure Rate
2(2)
Relation between Reliability and Mean-Time-Between-Failures
4(2)
Maintainability
6(2)
Availability
8(1)
Series and Parallel Systems
8(4)
Dependability
12(1)
References
12(3)
Error Detecting and Correcting Codes
15(28)
Parity Code
16(1)
Multiple Error Detecting Codes
17(10)
Unordered Codes for Unidirectional Error Detection
18(2)
t-unidirectional Error Detecting Codes
20(2)
Burst Unidirectional Error Detecting Code
22(5)
Residue Codes
27(1)
Cyclic Codes
28(2)
Error Correcting Codes
30(10)
Hamming Code
31(1)
Hsiao Code
31(5)
Reed-Solomon Code
36(4)
References
40(3)
Self-Checking Combinational Logic Design
43(36)
Strongly Fault-Secure Circuits
46(1)
Strongly Code-Disjoint Circuits
47(2)
Terminology
49(1)
Bidirectional Error-Free Combinational Circuit Design
50(3)
Detection of Input Fault Induced Bidirectional Errors
53(2)
Techniques for Bidirectional Error Elimination
55(6)
Input Encoding
55(3)
Output Encoding
58(3)
Self-Dual Parity Checking
61(4)
Self-Checking Design Using Low-Cost Residue Code
65(2)
Totally Self-Checking PLA Design
67(6)
Fail-Safe Combinational Circuit Design
73(3)
References
76(3)
Self-Checking Checkers
79(52)
The Two-Rail Checker
79(3)
Totally Self-Checking Checkers for m-out-of-n Codes
82(25)
Pass Transistor-Based Checker Design for a Subset of m-out-of-2m Codes
95(4)
Totally Self-Checking Checker for 1-out-of-n Code
99(8)
Totally Self-Checking Checker for Berger Code
107(19)
Totally Self-Checking Checker for Low-Cost Residue Code
126(2)
References
128(3)
Self-Checking Sequential Circuit Design
131(30)
Faults in State Machines
132(2)
Self-Checking State Machine Design Techniques
134(9)
Elimination of Bidirectional Errors
143(2)
Synthesis of Redundant Fault-Free State Machines
145(5)
Decomposition of Finite State Machines
150(2)
Self-Checking Interacting State Machine Design
152(4)
Fail-Safe State Machine Design
156(3)
References
159(2)
Fault-Tolerant Design
161(42)
Hardware Redundancy
162(14)
Static Redundancy
162(6)
Dynamic Redundancy
168(4)
Hybrid Redundancy
172(4)
Information Redundancy
176(11)
Fault-Tolerant State Machine Design Using Hamming Codes
176(2)
Error Checking and Correction (ECC) in Memory Systems
178(1)
Improvement in Reliability with ECC
179(2)
Multiple Error Correction Using Orthogonal Latin Squares Configuration
181(4)
Soft Error Correction Using the Horizontal and Vertical Parity Method
185(2)
Time Redundancy
187(1)
Software Redundancy
188(1)
System-Level Fault Tolerance
189(9)
Byzantine Fault Model
191(3)
System-Level Fault Detection
194(2)
Backward Recovery Schemes
196(1)
Forward Recovery Schemes
196(2)
References
198(5)
Appendix: Markov Models 203(2)
Index 205


The author is currently a Professor in the Department of Electrical Engineering at North Carolina A&T State University. He is the author of more than 75 papers, and three books published by Prentice Hall. His research interests include design for testability, self-checking logic design, automatic logic synthesis of low power logic circuits, andCPLD/FPGA based system design. He received a M.S. from King's College, London, and a Ph.D. from the City University of London.