Muutke küpsiste eelistusi

Signal Integrity Engineer's Companion: Real-Time Test and Measurement and Design Simulation [Kõva köide]

  • Formaat: Hardback, 496 pages, kõrgus x laius x paksus: 203x252x30 mm, kaal: 864 g
  • Ilmumisaeg: 09-Jul-2008
  • Kirjastus: Prentice Hall
  • ISBN-10: 0131860062
  • ISBN-13: 9780131860063
  • Kõva köide
  • Hind: 105,84 €*
  • * saadame teile pakkumise kasutatud raamatule, mille hind võib erineda kodulehel olevast hinnast
  • See raamat on trükist otsas, kuid me saadame teile pakkumise kasutatud raamatule.
  • Kogus:
  • Lisa ostukorvi
  • Tasuta tarne
  • Lisa soovinimekirja
  • Formaat: Hardback, 496 pages, kõrgus x laius x paksus: 203x252x30 mm, kaal: 864 g
  • Ilmumisaeg: 09-Jul-2008
  • Kirjastus: Prentice Hall
  • ISBN-10: 0131860062
  • ISBN-13: 9780131860063

A Signal Integrity Engineer’s Companion

Real-Time Test and Measurement and Design Simulation

Geoff Lawday

David Ireland

Greg Edlund

Foreword by Chris Edwards, Editor, IET Electronics Systems
and Software magazine

Prentice Hall Modern Semiconductor Design Series

Prentice Hall Signal Integrity Library

Use Real-World Test and Measurement Techniques to Systematically Eliminate Signal Integrity Problems

This is the industry’s most comprehensive, authoritative, and practical guide to modern Signal Integrity (SI) test and measurement for high-speed digital designs. Three of the field’s leading experts guide you through systematically detecting, observing, analyzing, and rectifying both modern logic signal defects and embedded system malfunctions. The authors cover the entire life cycle of embedded system design from specification and simulation onward, illuminating key techniques and concepts with easy-to-understand illustrations.

Writing for all electrical engineers, signal integrity engineers, and chip designers, the authors show how to use real-time test and measurement to address today’s increasingly difficult interoperability and compliance requirements. They also present detailed, start-to-finish case studies that walk you through commonly encountered design challenges, including ensuring that interfaces consistently operate with positive timing margins without incurring excessive cost; calculating total jitter budgets; and managing complex tradeoffs
in high-speed serial interface design.

Coverage includes

  • Understanding the complex signal integrity issues that arise in today’s high-speed designs
  • Learning how eye diagrams, automated compliance tests, and signal analysis measurements can help you identify and solve SI problems
  • Reviewing the electrical characteristics of today’s most widely used CMOS IO circuits
  • Performing signal path analyses based on intuitive Time-Domain Reflectometry (TDR) techniques
  • Achieving more accurate real-time signal measurements and avoiding probe problems and artifacts
  • Utilizing digital oscilloscopes and logic analyzers to make accurate measurements in high-frequency environments
  • Simulating real-world signals that stress digital circuits and expose SI faults
  • Accurately measuring jitter and other RF parameters in wireless applications

About the Authors: Dr. Geoff Lawday is Tektronix Professor in Measurement at Buckinghamshire New University, England. He delivers courses in signal integrity engineering and high performance bus systems at the University Tektronix laboratory, and presents signal integrity seminars throughout Europe on behalf of Tektronix. David Ireland, European and Asian design and manufacturing marketing manager for Tektronix, has more than 30 years of experience in test and measurement. He writes regularly on signal integrity for leading technical journals. Greg Edlund, Senior Engineer, IBM Global Engineering Solutions division, has participated in development and testing for ten high-performance computing platforms. He authored Timing Analysis and Simulation for Signal Integrity Engineers (Prentice Hall).

Muu info

A Signal Integrity Engineers Companion

 

Real-Time Test and Measurement and Design Simulation

 

Geoff Lawday

David Ireland

Greg Edlund

 

Foreword by Chris Edwards, Editor, IET Electronics Systems and Software magazine

 

Prentice Hall Modern Semiconductor Design Series

Prentice Hall Signal Integrity Library

 

Use Real-World Test and Measurement Techniques to Systematically Eliminate Signal Integrity Problems

 

 

This is the industrys most comprehensive, authoritative, and practical guide to modern Signal Integrity (SI) test and measurement for high-speed digital designs. Three of the fields leading experts guide you through systematically detecting, observing, analyzing, and rectifying both modern logic signal defects and embedded system malfunctions. The authors cover the entire life cycle of embedded system design from specification and simulation onward, illuminating key techniques and concepts with easy-to-understand illustrations.

 

Writing for all electrical engineers, signal integrity engineers, and chip designers, the authors show how to use real-time test and measurement to address todays increasingly difficult interoperability and compliance requirements. They also present detailed, start-to-finish case studies that walk you through commonly encountered design challenges, including ensuring that interfaces consistently operate with positive timing margins without incurring excessive cost; calculating total jitter budgets; and managing complex tradeoffs in high-speed serial interface design.

 

Coverage includes





Understanding the complex signal integrity issues that arise in todays high-speed designs Learning how eye diagrams, automated compliance tests, and signal analysis measurements can help you identify and solve SI problems Reviewing the electrical characteristics of todays most widely used CMOS IO circuits Performing signal path analyses based on intuitive Time-Domain Reflectometry (TDR) techniques Achieving more accurate real-time signal measurements and avoiding probe problems and artifacts Utilizing digital oscilloscopes and logic analyzers to make accurate measurements in high-frequency environments Simulating real-world signals that stress digital circuits and expose SI faults Accurately measuring jitter and other RF parameters in wireless applications

 

About the Authors: Dr. Geoff Lawday is Tektronix Professor in Measurement at Buckinghamshire New University, England. He delivers courses in signal integrity engineering and high performance bus systems at the University Tektronix laboratory, and presents signal integrity seminars throughout Europe on behalf of Tektronix. David Ireland, European and Asian design and manufacturing marketing manager for Tektronix, has more than 30 years of experience in test and measurement. He writes regularly on signal integrity for leading technical journals. Greg Edlund, Senior Engineer, IBM Global Engineering Solutions division, has participated in development and testing for ten high-performance computing platforms. He authored Timing Analysis and Simulation for Signal Integrity Engineers (Prentice Hall).

 

 
Foreword xv
Preface xix
Acknowledgments xxviii
About the Authors xxx
Introduction: An Engineer's Companion
1(30)
Life Cycle: The Motivation to Develop a Simulation Strategy
2(7)
Prototyping: Interconnecting High-Speed Digital Signals
9(4)
Pre-emphasis
13(4)
The Need for Real-Time Test and Measurement
17(14)
Conclusion
28(3)
Chip-to-Chip Timing and Simulation
31(56)
Root Cause
32(1)
CMOS Latch
32(3)
Timing Failures
35(1)
Setup and Hold Constraints
36(4)
Common-Clock On-Chip Timing
40(2)
Setup and Hold SPICE Simulations
42(1)
Timing Budget
43(2)
Common-Clock IO Timing
45(4)
Common-Clock IO Timing Using a Standard Load
49(5)
Limits of the Common-Clock Architecture
54(1)
Inside IO Circuits
54(1)
CMOS Receiver
55(2)
CMOS Differential Receiver
57(1)
Pin Capacitance
58(2)
Receiver Current-Voltage Characteristics
60(1)
CMOS Push-Pull Driver
61(2)
Output Impedance
63(1)
Output Rise and Fall Times
64(2)
CMOS Current Mode Driver
66(2)
Behavioral Modeling of IO Circuits
68(1)
Behavioral Model for CMOS Push-Pull Driver
69(2)
Behavioral Modeling Assumptions
71(1)
Tour of an IBIS Model
71(5)
IBIS Header
76(1)
IBIS Pin Table
76(1)
IBIS Receiver Model
77(1)
IBIS Driver Model
78(2)
Behavioral Modeling Assumptions (Reprise)
80(1)
Comparison of SPICE and IBIS Models
81(2)
Accuracy and Quality of IO Circuit Models
83(4)
Conclusion
86(1)
Signal Path Analysis as an Aid to Signal Integrity
87(30)
The Transmission Line Environment
89(3)
Characteristic Impedance, Reflections, and Signal Integrity
92(5)
The Reflection Coefficient, Impedance, and TDR Concepts
97(6)
Looking at Real-World Circuit Characteristics
103(1)
TDR Resolution Factors
104(5)
Differential TDR Measurements
109(2)
Frequency Domain Measurements for SI Applications
111(6)
Conclusion
115(2)
DDR2 Case Study
117(42)
Evolution from a Common Ancestor
118(3)
DDR2 Signaling
121(2)
Write Timing
123(2)
Read Timing
125(2)
Get to Know Your IO
127(1)
Off-Chip Driver
128(1)
On-Die Termination
129(2)
Rising and Falling Waveforms
131(1)
Interconnect Sensitivity Analysis
132(3)
Conductor and Dielectric Losses
135(3)
Impedance Tolerance
138(4)
Pin-to-Pin Capacitance Variation
142(1)
Length Variation within a Byte Lane
142(1)
DIMM Connector Crosstalk
143(4)
Vref AC Noise and Resistor Tolerance
147(2)
Slope Derating Factor
149(1)
Final Read and Write Timing Budgets
149(5)
Sources of Conservatism
154(5)
Conclusion
155(4)
Real-Time Measurements: Probing
159(54)
The Anatomy of a Modern Oscilloscope Probe
160(3)
A Probing Strategy
163(1)
Measurement Quality
164(1)
Defining a Probe
164(2)
Oscilloscope Probes
166(6)
Dynamic Range Limitations
172(15)
Advanced Probing Techniques
187(21)
Logic Analyzer Probing
208(5)
Conclusion
212(1)
Testing and Debugging: Oscilloscopes and Logic Analyzers
213(42)
Fundamentals of Signal Integrity
214(1)
Signal Integrity Concepts
215(6)
Verification Tools: Oscilloscopes
221(6)
Verification Tools: Logic Analyzers
227(18)
Combining Analog and Digital Measurements
245(6)
Eye Diagram Analysis
251(4)
Conclusion
253(2)
Replicating Real-World Signals with Signal Sources
255(32)
Observing and Controlling Circuit Behavior
256(1)
Excitation and Control
257(2)
Signal-Generation Techniques
259(2)
Arbitrary Function Generator
261(8)
The Arbitrary Waveform Generator
269(12)
Logic Signal Sources
281(6)
Conclusion
285(2)
Signal Analysis and Compliance
287(80)
Standards Framework
288(5)
High-Performance Tools for Compliance Measurements
293(3)
Validation and Compliance Measurements
296(1)
Understanding Serial Architectures
297(9)
Physical Layer Compliance Testing
306(6)
Measurements on Optical Signals
312(3)
Compliance Measurement Considerations: Analysis
315(4)
Testing the Serial Link
319(6)
Probes and Probing
325(3)
Software Tools
328(4)
Transmitter Measurement Examples
332(2)
Impedance and Link Measurements
334(11)
Receiver Testing Brings Unique Challenges
345(11)
Digital Validation and Compliance
356(5)
Multibus Systems
361(6)
Conclusion
364(3)
PCI Express Case Study
367(32)
High-Speed Serial Interfaces
368(3)
Sensitivity Analysis
371(2)
Ideal Driver and Lossy Transmission Line
373(2)
Differential Driver with De-emphasis
375(4)
Card Impedance Tolerance
379(2)
3D Discontinuities
381(2)
Channel Step Response
383(3)
Crosstalk Pathology
386(1)
Crosstalk-Induced Jitter
387(5)
Channel Characteristics
392(1)
Sensitivity Analysis Results
393(3)
Model-to-Hardware Correlation
396(3)
Conclusion
398(1)
The Wireless Signal
399(40)
Radio Frequency Signals
400(2)
Frequency Measurement
402(5)
Overview of the Real-Time Spectrum Analyzer
407(6)
How a Real-Time Spectrum Analyzer Works
413(4)
Applying Real-Time Spectrum Analysis
417(22)
Conclusion
437(2)
Index 439
Dr. Geoffrey Lawday currently holds the Tektronix Chair in Measurement at Buckinghamshire New University where he teaches embedded system design and high performance computing in the School of Computing. Having gained a BSc in Physics and an MSc in Computer Engineering at Surrey University, he was awarded a PhD in Time-Frequency Signal Analysis from Brunel University. His research in signal integrity engineering is reflected in his publications, such as the critique on the introduction of the new serial buses published in the flagship journal of the Institution of Electrical Engineers.

 

David Ireland has more than thirty years experience in test and measurement ranging from an engineering apprenticeship with Racal, where he gained his formal electronic engineering qualifications, to his current position at Tektronix, where he is the marketing manager of design and manufacturing at Tektronix Europe. He is widely recognized by embedded system engineers in Europe for his signal integrity articles and collaborative workshops on high-speed digital system design, test, and measurement.

 

Greg Edlunds career in signal integrity began in 1988 at Supercomputer Systems, Inc., where he simulated and measured timing characteristics of bipolar embedded RAMs used in the computers vector registers. Since then, he has participated in the development and testing of nine other high-performance computing platforms for Cray Research, Inc., Digital Equipment Corp., and IBM Corp. He has had the good fortune of learning from many talented engineers while focusing his attention on modeling, simulation, and measurement of IO circuits and interconnect components. A solid physical foundation and practical engineering experience combine to form a valuable perspective on optimizing performance, reliability, and cost.