Foreword |
|
v | |
|
|
|
Chapter 1 System Architecture |
|
|
|
|
|
|
3 | (2) |
|
1.2 Wireless Communication Systems |
|
|
5 | (4) |
|
1.3 WLAN Transceiver Architecture |
|
|
9 | (8) |
|
|
16 | (1) |
|
Chapter 2 Digital Baseband |
|
|
|
|
|
|
|
17 | (2) |
|
2.2 Scrambling/Descrambling |
|
|
19 | (2) |
|
2.3 Channel Coding and Error Correction |
|
|
21 | (10) |
|
2.4 Interleaving/Deinterleaving |
|
|
31 | (5) |
|
|
36 | (1) |
|
|
37 | (2) |
|
|
39 | (2) |
|
|
41 | (1) |
|
|
42 | (2) |
|
|
44 | (9) |
|
|
53 | (5) |
|
|
58 | (3) |
|
|
59 | (2) |
|
Chapter 3 Analog Front-End |
|
|
|
|
|
|
61 | (8) |
|
3.2 Specifying Transceiver |
|
|
69 | (7) |
|
3.3 Transmitter Architecture |
|
|
76 | (7) |
|
3.4 Receiver Architectures |
|
|
83 | (14) |
|
|
92 | (5) |
|
|
|
|
|
|
|
|
|
97 | (3) |
|
|
100 | (3) |
|
|
103 | (4) |
|
|
107 | (4) |
|
|
107 | (4) |
|
Chapter 5 Digital Circuit Models |
|
|
|
|
|
|
|
111 | (1) |
|
5.2 General Purpose Processors |
|
|
112 | (9) |
|
5.3 Digital Signal Processors |
|
|
121 | (35) |
|
|
156 | (1) |
|
|
156 | (1) |
|
|
157 | (1) |
|
|
158 | (7) |
|
|
162 | (3) |
|
Chapter 6 AMS Circuit Budgets |
|
|
|
|
|
|
165 | (1) |
|
6.2 From High-Level Specifications to Low(er)-level Requirements |
|
|
166 | (22) |
|
6.3 Budgeting the Transceiver |
|
|
188 | (11) |
|
|
196 | (3) |
|
Chapter 7 Embedded Memories |
|
|
|
|
|
199 | (1) |
|
7.2 Memory Systems: Current Landscape |
|
|
200 | (5) |
|
|
205 | (14) |
|
|
219 | (6) |
|
|
219 | (6) |
|
Part 3 Implementation and Integration |
|
|
|
Chapter 8 Implementation Methodologies |
|
|
|
|
|
|
225 | (1) |
|
8.2 Semi-Custom Methodology |
|
|
226 | (13) |
|
8.3 Full-Custom Methodology |
|
|
239 | (4) |
|
|
241 | (2) |
|
Chapter 9 Semi-Custom Implementation of Digital Circuits |
|
|
|
|
|
|
243 | (1) |
|
|
244 | (7) |
|
9.3 Digital Baseband Processor |
|
|
251 | (12) |
|
|
262 | (1) |
|
Chapter 10 Full-Custom Implementation of Analog and Mixed-Signal Circuits |
|
|
|
|
|
|
263 | (2) |
|
10.2 Technology Selection |
|
|
265 | (6) |
|
10.3 AMS-RF Top-Level Implementation |
|
|
271 | (14) |
|
|
282 | (3) |
|
|
|
|
|
|
|
285 | (1) |
|
|
286 | (6) |
|
|
292 | (5) |
|
11.4 RF-MIMO Transceiver Example |
|
|
297 | (14) |
|
|
307 | (4) |
|
Part 4 Verification and Testing |
|
|
|
|
|
|
|
311 | (4) |
|
12.2 Verification Process |
|
|
315 | (9) |
|
12.3 Verification Techniques |
|
|
324 | (3) |
|
|
327 | (2) |
|
|
329 | (5) |
|
|
334 | (4) |
|
|
338 | (3) |
|
|
338 | (3) |
|
Chapter 13 Digital Testing |
|
|
|
|
|
341 | (2) |
|
13.2 Test for What? Defects and Fault Modelling |
|
|
343 | (3) |
|
13.3 Which Test Sequence Do I have to Apply? Test Generation |
|
|
346 | (9) |
|
13.4 How the Test Sequence is Applied? Design-for-Test |
|
|
355 | (3) |
|
|
358 | (3) |
|
|
358 | (3) |
|
Chapter 14 Analog, Mixed-Signal, and RF Circuits Test |
|
|
|
|
|
361 | (1) |
|
14.2 System-Level Considerations |
|
|
362 | (3) |
|
14.3 Performance-Oriented Testing |
|
|
365 | (12) |
|
14.4 Defect-Oriented Testing |
|
|
377 | (10) |
|
|
383 | (4) |
|
Chapter 15 Embedded Memory Test |
|
|
|
|
|
|
387 | (1) |
|
|
387 | (6) |
|
|
393 | (5) |
|
15.4 Test Challenges of Emerging Memories |
|
|
398 | (7) |
|
|
402 | (3) |
Index |
|
405 | |