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Smart and Flexible Digital-to-Analog Converters 2011 ed. [Kõva köide]

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  • Formaat: Hardback, 310 pages, kõrgus x laius: 235x155 mm, kaal: 1390 g, XIV, 310 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 15-Jan-2011
  • Kirjastus: Springer
  • ISBN-10: 9400703465
  • ISBN-13: 9789400703469
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Smart and Flexible Digital-to-Analog Converters 2011 ed.Suurem pilt
  • Formaat: Hardback, 310 pages, kõrgus x laius: 235x155 mm, kaal: 1390 g, XIV, 310 p., 1 Hardback
  • Sari: Analog Circuits and Signal Processing
  • Ilmumisaeg: 15-Jan-2011
  • Kirjastus: Springer
  • ISBN-10: 9400703465
  • ISBN-13: 9789400703469
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9789400703469.html
Märksõnad:
Smart and Flexible Digital-to-Analog Converters proposes new concepts and implementations for flexibility and self-correction of current-steering digital-to-analog converters (DACs) which allow the attainment of a wide range of functional and performance specifications, with a much reduced dependence on the fabrication process. DAC linearity is analysed with respect to the accuracy of the DAC unit elements. A classification is proposed of the many different current-steering DAC correction methods. The classification reveals methods that do not yet exist in the open literature. Further, this book systematically analyses self-calibration correction methods for the various DAC mismatch errors. For instance, efficient calibration of DAC binary currents is identified as an important missing method. This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance. Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.DAC linearity is analysed with respect to the accuracy of the DAC unit elements. A classification is proposed of the many different current-steering DAC correction methods. The classification reveals methods that do not yet exist in the open literature. Further, this book systematically analyses self-calibration correction methods for the various DAC mismatch errors. For instance, efficient calibration of DAC binary currents is identified as an important missing method. This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance. Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance. Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.

With proposals for new concepts in the flexibility and self-correction of DACs that should enable a range of functional and performance specifications, this book's detailed coverage is ideal for seasoned professionals and newcomers to the field alike.

Arvustused

From the reviews:

This is a very useful book on the state of the art in the field of digital-to-analog conversion (DAC) methods whose main aim is to advance the existing knowledge on efficient and robust high-performance current-steering DACs, and to investigate the concept of DAC flexibility. The authors focus on the accuracy and they stress DAC correction methods to achieve it and to provide high efficiency. The list of references contains 94 items, most of them published recently. (Vladimir ade, Zentralblatt MATH, Vol. 1217, 2011)

Part I Introduction and Basics
1(30)
1 Introduction
3(8)
1.1 Modern Micro-electronics and Flexibility
3(2)
1.2 Aims of the Book
5(1)
1.3 Scope of the Book
6(1)
1.4 Scientific Approach
6(1)
1.5 Outline of the Book
7(4)
2 Basics of Digital-to-Analog Conversion
11(20)
2.1 Introduction
11(1)
2.2 Functionality and Specifications
12(4)
2.2.1 Static Characterization
12(3)
2.2.2 Dynamic Characterization
15(1)
2.3 DAC Resources
16(2)
2.4 Segmentation of DAC Analog Resources
18(5)
2.4.1 Binary Algorithmic Segmentation
19(1)
2.4.2 Sub-binary Radix Algorithmic Segmentation
20(1)
2.4.3 Unary Algorithmic Segmentation
21(1)
2.4.4 Binary LSB and Unary MSB Algorithmic Segmentation
22(1)
2.5 DAC Implementations
23(2)
2.6 Current-Steering DAC Architecture
25(1)
2.7 Modern Current-Steering DAC Challenges
26(3)
2.8 Summary
29(2)
Part II State-of-the-Art Correction Methods
31(26)
3 Error Correction by Design
33(10)
3.1 Introduction
33(1)
3.2 Return-to-Zero Output
34(2)
3.3 Differential-Quad Switching
36(1)
3.4 Cascode Switches with Offset Current
37(1)
3.5 Input Data Reshuffling Methods (DEM)
38(3)
3.6 Discussion
41(1)
3.7 Conclusions
41(2)
4 Smart Self-Correcting D/A Converters
43(14)
4.1 Introduction
43(1)
4.2 Self-Calibration of DAC Current Cells
44(3)
4.2.1 Amplitude Errors Self-Calibration
45(1)
4.2.2 Timing Errors Self-Calibration
46(1)
4.2.3 Discussion
47(1)
4.3 Mapping
47(6)
4.3.1 Low Level Maps for DAC Unary Current Cells
48(3)
4.3.2 Low-Level Maps for Sub-binary Radix DACs
51(2)
4.4 Digital Pre-distortion
53(1)
4.5 Discussion
54(1)
4.6 Conclusions
55(2)
Part III New Modeling, Analysis, and Classification
57(72)
5 Error Modeling for DAC Correction, a Broad View
59(12)
5.1 Introduction
59(2)
5.2 A Model of the Step Response of a Current Cell
61(1)
5.3 Transistor Mismatch Caused Errors
62(4)
5.4 Digital-Switching Errors
66(2)
5.5 Discussion
68(2)
5.6 Conclusions
70(1)
6 Brownian Bridge Based Analysis and Modeling of DAC Linearity, an In-depth View
71(14)
6.1 Introduction
71(2)
6.2 New Statistical Analysis of the DAC Static Non-linearity Based on Brownian Bridge
73(8)
6.2.1 Unary DAC
74(4)
6.2.2 Binary DAC
78(3)
6.3 Discussion
81(2)
6.4 Conclusions
83(2)
7 Classification of Error Correction Methods, a Broad View
85(10)
7.1 Introduction
85(1)
7.2 Selected Set of DAC Correction Methods and Definitions
86(2)
7.3 Error Measurement Category
88(3)
7.4 Redundancy Category
91(1)
7.5 System Level Category
92(1)
7.6 Discussion
93(1)
7.7 Conclusion
94(1)
8 Analysis of Self-Calibration of Currents, an In-depth View
95(34)
8.1 Introduction
95(1)
8.2 DAC Currents Self-Calibration Classification
96(2)
8.3 Self-Measurement
98(15)
8.3.1 Measurement Probes
98(6)
8.3.2 Reference
104(1)
8.3.3 Measurement Device
105(8)
8.4 Algorithm
113(8)
8.4.1 Unary-Currents Calibration
113(3)
8.4.2 New Binary-Currents Calibration in a Unary Way
116(1)
8.4.3 New True Binary-Currents Calibration
117(4)
8.5 Self-Correction
121(5)
8.5.1 Self-Correction Method
121(2)
8.5.2 Correction Circuits
123(2)
8.5.3 Correction Memory
125(1)
8.6 Conclusions
126(3)
Part IV New Concepts and Methods
129(82)
9 New Redundant Segmentation Concept
131(10)
9.1 Introduction
131(3)
9.2 Abstraction Levels of Segmentation
134(2)
9.3 New Redundant Segmentation
136(3)
9.4 Discussion
139(1)
9.5 Conclusion
140(1)
10 New Methods for Self-Calibration of Currents
141(18)
10.1 Introduction
141(1)
10.2 Self-Calibration of Unary Currents
142(6)
10.2.1 New Calibration Method
142(6)
10.2.2 Conclusions
148(1)
10.3 A Calibration Method for Generic Current-Steering D/A Converters with Optimal Area Solution
148(5)
10.3.1 New Self-Calibrating Current Cell for a Generic DAC Architecture
149(1)
10.3.2 Area Driven Optimum of the Level of Calibration
150(2)
10.3.3 Discussion
152(1)
10.3.4 Conclusions
153(1)
10.4 A Calibration Method for Binary Signal Current Sources
153(4)
10.4.1 Calibration of Scaled Currents
154(3)
10.4.2 Conclusions
157(1)
10.5 Discussion
157(1)
10.6 Conclusions
157(2)
11 New Redundant Decoder Concept
159(10)
11.1 Introduction
159(1)
11.2 Conventional Row-Column Decoder
160(1)
11.3 New Decoder with Redundancy
161(3)
11.4 Simulation Results
164(2)
11.5 Discussion
166(2)
11.6 Conclusions
168(1)
12 New High-Level Mapping Concept
169(8)
12.1 Introduction
169(1)
12.2 Conceptual Idea
170(2)
12.3 Illustrative Measurement and Simulation Results for Amplitude Errors Mapping
172(2)
12.4 Limitations and Discussion
174(1)
12.5 Conclusions
175(2)
13 New Harmonic-Distortion-Suppression Method
177(8)
13.1 Introduction
177(1)
13.2 Theoretical Background
178(2)
13.3 Application Area
180(2)
13.3.1 Phase-Shifters
180(2)
13.3.2 Parallel Sub-DACs
182(1)
13.3.3 Candidate Applications
182(1)
13.4 Limitations and Discussion
182(1)
13.5 Conclusions
183(2)
14 Flexible Digital-to-Analog Converters Concept
185(26)
14.1 Introduction
185(1)
14.2 Flexible DAC Platform
186(1)
14.3 Definitions of Flexibility
187(4)
14.3.1 Hardware Flexibility: Configurability
188(2)
14.3.2 Flexible Op-Modes (Software Flexibility): Programmability
190(1)
14.4 Operation Modes
191(17)
14.4.1 General Flexibility
193(11)
14.4.2 Special Op-Modes with DAC Correction Methods
204(4)
14.5 The "Missing Code Problem"
208(1)
14.6 Conclusions
209(2)
Part V Design Examples
211(80)
15 A Redundant Binary-to-Thermometer Decoder Design
213(8)
15.1 Introduction
213(2)
15.2 Design Example
215(2)
15.3 Measurement Results and Discussion
217(3)
15.4 Conclusions
220(1)
16 Two Self-Calibrating DAC Designs
221(26)
16.1 Introduction
221(1)
16.2 Unary Currents Self-Calibration in a 250 nm DAC
222(9)
16.2.1 Design
223(2)
16.2.2 Measurements
225(5)
16.2.3 Temperature Effects
230(1)
16.3 Both Unary and Binary Currents Self-Calibration in a 180 nm DAC
231(10)
16.3.1 Design
233(3)
16.3.2 Measurements
236(5)
16.4 Comparison with State-of-the-Art DAC Publications
241(1)
16.5 Conclusions
242(5)
17 A Functional-Segmentation DAC Design Using Harmonic Distortion Suppression Method
247(12)
17.1 Introduction
247(1)
17.2 Test Set-up Design
248(1)
17.3 Parallel Virtual DACs
249(4)
17.4 Parallel Real Sub-DACs
253(2)
17.5 OFDM (Multi-tone) System Application
255(1)
17.6 Conclusions
256(3)
18 A 14 Bit Quad Core Flexible 180 nm DAC Platform
259(10)
18.1 Introduction
259(1)
18.2 Design
260(2)
18.3 Measurements
262(5)
18.4 Conclusions
267(2)
19 A 16 bit 16-core Flexible 40 nm DAC Platform
269(22)
19.1 Introduction
269(1)
19.2 Flexible DAC Platform Based on 16 Core Units
270(3)
19.3 Measurements
273(16)
19.3.1 The 12-bit sub-DAC Performance
273(7)
19.3.2 The High Resolution Flexible DAC Performance
280(9)
19.4 Conclusions
289(2)
Summary 291(4)
Conclusion 295(2)
Appendix 297(8)
References 305
Georgi Radulov was born in Plovdiv, Bulgaria in 1978. He received the M.Sc. engineer (èíæ.) degree in electrical engineering in 2001 from the Technical University of Sofia (TU-Sofia), Bulgaria. In 2004, he received the degree Professional Doctorate in Engineering (PDEng) from Stan Ackermans Institute at Eindhoven University of Technology (TU/e). He received his Ph.D. degree from TU/e in 2010.  From 1999 until 2001, he was a student assistant at ECAD Lab of TU-Sofia. Since August 2001, he is member of the Mixed-Signal Microelectronics (MsM) Group at TU/e. Since 2009, he is a part-time Assistant Professor at the Electrical Engineering faculty of TU/e and a part-time director of the micro-electronics consultancy company Welikan B.V. Georgi Radulov holds 2 US patents on current calibration. In 2008, he was awarded the Outstanding Student Paper of the IEEE conference APCCAS 2008, in Macau. Georgi Radulov has more than 20 publications on Digital-to-Analog Converters.

Patrick John Quinn graduated in Electronic Engineering at University College Dublin with a B.E. degree in 1986 and M.Sc. (Eng.) degree in 1989. The M.Sc. thesis was entitled Design and investigation of a direct conversion FM receiver and its application in mobile radio. The research for the thesis was carried out in the Mobile Telephony group at Philips Semiconductors in Eindhoven. He received his Ph.D. degree in TU/e in 2006. His Ph.D. thesis was entitled High-accuracy switched-capacitor techniques applied to filter and ADC design. From 1989 to 2000, he was employed at the Philips Semiconductors Advanced Systems Lab in Eindhoven. There he worked in various roles from IC design engineer to project leader in the areas of mobile telephony, video and radio systems and circuits. Most projects were based on analogue sampled-data processing, usually using switched capacitor circuit techniques for implementation. At the end of 2000, he joined the mixed-signalcentre-of-expertise of Xilinx at European HQ in Dublin, Ireland. There he is team leader and technical lead of advanced mixed-signal IC design projects for Virtex FPGAs down to 32nm CMOS. These are the first mixed-signal systems to enter into full 32nm production of any company in the world. He author has a range of professional publications and international patents. He has had a long association with the research activities of the Mixed-Signal Microelectronics department of the Eindhoven University of Technology.

Johannes A. (Hans) Hegt (M97, SM2001) was born on June 30, 1952 in Amsterdam, the Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology (TU/e), where he graduated with honors in 1982.  From 1983 until 1986 he was an assistant at the TU/e. Since 1987, he is a lecturer at this University, where he gives courses in the areas of switched-capacitor filter engineering, switched current filters, digital electronics, microprocessors, digital signal processing, neural networks, non-linear systems and mixed-signal systems. In 1988 he received a Ph.D. degree on synthesis of switched-capacitor filters. Since 1994 he is an Associate Professor on mixed analogue/digital circuit design. He is currently especially involved in the hardware realization of ADCs and DACs.

Arthur H.M. van Roermund (SM95) was born in Delft, The Netherlands in 1951. He received the M.Sc. degree in electrical engineering in 1975 from the Delft University of Technology and the Ph.D. degree in Applied Sciences from the K.U.Leuven, Belgium, in 1987. From 1975 to 1992 he was with Philips Research Laboratories in Eindhoven. From 1992 to 1999 he has been a full professor at the Electrical Engineering Department of Delft University of Technology, where he was chairman of the Electronics Research Group and member of the management team of DIMES. From 1992 to 1999 he has been chairman of a two-years post-graduate school forchartered designer. From 1992 to 1997 he has been consultant for Philips. October 1999 he joined Eindhoven University of Technology as a full professor, chairing the Mixed-signal Microelectronics Group. Since September 2002 he is also director of research of the Department of Electrical Engineering. He is chairman of the board of ProRISC, a nation-wide microelectronics platform; a member of the ICT research platform for the Netherlands (IPN); and a member of the supervisory board of the NRC Photonics research centre. Since 2001, he is one of the three organisers of the yearly workshop on Advanced Analog Circuit Design (AACD). In 2004 he achieved the Simon Stevin Meester award, coupled to a price of 500.000, for his scientific and technological achievements. In 2007 he was member of an international assessment panel for the Department of Electronics and Information of Politecnico di Milano, and in 2009 for Electronics and Electrical Engineering for the merged Aalto University Finland. He authored/co-authored more than 300 articles and 25 books.