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SOC Design Methodologies: IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC01) December 35, 2001, Montpellier, France Softcover reprint of the original 1st ed. 2002 [Pehme köide]

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  • Formaat: Paperback / softback, 480 pages, kõrgus x laius: 235x155 mm, kaal: 753 g, XX, 480 p., 1 Paperback / softback
  • Sari: IFIP Advances in Information and Communication Technology 90
  • Ilmumisaeg: 06-Mar-2013
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1475765304
  • ISBN-13: 9781475765304
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  • Pehme köide
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  • Formaat: Paperback / softback, 480 pages, kõrgus x laius: 235x155 mm, kaal: 753 g, XX, 480 p., 1 Paperback / softback
  • Sari: IFIP Advances in Information and Communication Technology 90
  • Ilmumisaeg: 06-Mar-2013
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1475765304
  • ISBN-13: 9781475765304
Teised raamatud teemal:
The 11 th IFIP International Conference on Very Large Scale Integration, in Montpellier, France, December 3-5,2001, was a great success. The main focus was about IP Cores, Circuits and System Designs & Applications as well as SOC Design Methods and CAD. This book contains the best papers (39 among 70) that have been presented during the conference. Those papers deal with all aspects of importance for the design of the current and future integrated systems. System on Chip (SOC) design is today a big challenge for designers, as a SOC may contain very different blocks, such as microcontrollers, DSPs, memories including embedded DRAM, analog, FPGA, RF front-ends for wireless communications and integrated sensors. The complete design of such chips, in very deep submicron technologies down to 0.13 mm, with several hundreds of millions of transistors, supplied at less than 1 Volt, is a very challenging task if design, verification, debug and industrial test are considered. The microelectronic revolution is fascinating; 55 years ago, in late 1947, the transistor was invented, and everybody knows that it was by William Shockley, John Bardeen and Walter H. Brattein, Bell Telephone Laboratories, which received the Nobel Prize in Physics in 1956. Probably, everybody thinks that it was recognized immediately as a major invention.

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Springer Book Archives
Architecture for Signal & Image Processing.- Two ASIC for Low and Middle
Levels of Real Time Image Processing.- 64 × 64 Pixels General Purpose Digital
Vision Chip.- A Vision System on Chip for Industrial Control.- Fast Recursive
Implementation of the Gaussian Filter.- Dynamically Re-configurable
Architectures.- A Dynamically Reconfigurable Architecture for Low-Power
Multimedia Terminals.- Dynamically Reconfigurable Architectures for Digital
Signal Processing Applications.- Reconfigurable Architecture Using High Speed
FPGA.- CAD Tools.- Design Technology for Systems-on-Chip.- Distributed
Collaborative Design over Cave2 Framework.- High Performance Java Hardware
Engine and Software Kernel for Embedded Systems.- An Object-Oriented
Methodology for Modeling the Precise Behavior of Processor Architectures.-
Interconnect Capacitance Modelling in a VDSM CMOS Technology.- IP Design &
Reuse.- Abstract Communication Model and Automatic Interface generation for
IP integration in Hardware/Software Co-design.- An Evolutionary Approach for
Pareto-optimal Configurations in SOC Platforms.- Design of a Branch-Based
Carry-Select Adder IP Portable in 0.25 ?m Bulk and Silicon-On-Insulator CMOS
Technologies.- High Level Design Methodologies.- A Standardized Co-simulation
Backbone.- Automatic Code-Transformation and Architecture Refinement for
Application-Specific Multiprocessor SoCs with Shared Memory.- Power Issues.-
Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical
Model.- Power Consumption Model for the DSP OAK Processor.- Design for
Specific Constraints.- Integration of Robustness in the Design of a Cell.-
Impact of Technology Spreading on MEMS design Robustness.- Architectures.- A
New Efficient VLSI Architecture for Full Search Block Matching Motion
Estimation.-Design Considerations of a Low-Complexity, Low-Power Integer
Turbo Decoder.- Low Power, Low Voltage.- Low-Voltage Embedded-RAM Technology:
Present and Future.- Low-Voltage 0,25 ?m CMOS Improved Power Adaptive Issue
Queue for Embedded Microprocessors.- Gate Sizing for Low Power Design.-
Timing Issues.- Modeling and Design of Asynchronous Priority Arbiters for
On-Chip Communication Systems.- Feasible Delay Bound Definition.- Advance in
Mixed Signal.- CMOS Mixed-signal Circuits Design on a Digital Array Using
Minimum Transistors.- A VHDL-AMS Case Study: The Incremental Design of an
Efficient 3rd Generation MOS Model of a Deep Sub Micron Transistor.-
Verification & Validation.- Speeding Up Verification of RTL Designs by
Computing One-to-one Abstractions with Reduced Signal Widths.- Functional
Test Generation using Constraint Logic Programming.- Test.- An Industrial
Approach to Core-Based System Chip Testing.- Power-Constrained Test
Scheduling for SoCs Under a no session Scheme.- Random Adjacent Sequences:
An Efficient Solution for Logic BIST.- On-chip Generator of a Saw-Tooth Test
Stimulus for ADC BIST.- Built-in Test of Analog Non-Linear Circuits in a SOC
Environment.- Sensors.- Design of a Fast CMOS APS Imager for High Speed Laser
Detections.- Noise optimisation of a piezoresistive CMOS MEMS for magnetic
field sensing.- Authors Index.- Keywords Index.