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Soft Error Mechanisms, Modeling and Mitigation 1st ed. 2016 [Kõva köide]

  • Formaat: Hardback, 105 pages, kõrgus x laius: 235x155 mm, kaal: 454 g, 35 Illustrations, color; 46 Illustrations, black and white; XI, 105 p. 81 illus., 35 illus. in color., 1 Hardback
  • Ilmumisaeg: 04-Mar-2016
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319306065
  • ISBN-13: 9783319306063
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Soft Error Mechanisms, Modeling and Mitigation 1st ed. 2016Suurem pilt
  • Formaat: Hardback, 105 pages, kõrgus x laius: 235x155 mm, kaal: 454 g, 35 Illustrations, color; 46 Illustrations, black and white; XI, 105 p. 81 illus., 35 illus. in color., 1 Hardback
  • Ilmumisaeg: 04-Mar-2016
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319306065
  • ISBN-13: 9783319306063
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783319306063.html
Märksõnad:
Thisbook introduces readers to various radiation soft-error mechanisms such as softdelays, radiation induced clock jitter and pulses, and single event (SE)coupling induced effects. In addition to discussing various radiation hardeningtechniques for combinational logic, the author also describes new mitigationstrategies targeting commercial designs. Coverage includes novel soft errormitigation techniques such as the Dynamic Threshold Technique and Soft ErrorFiltering based on Transmission gate with varied gate and body bias. The discussion also includes modeling of SEcrosstalk noise, delay and speed-up effects. Various mitigation strategies toeliminate SE coupling effects are also introduced. Coverage also includes the reliability of lowpower energy-efficient designs and the impact of leakage power consumptionoptimizations on soft error robustness. The author presents an analysis of various power optimization techniques,enabling readers to make design choices that reduc

e static power consumptionand improve soft error reliability at the same time. 

Introduction.-Mitigation of Single Event Effects.- Transmission Gate (TG) Based Soft ErrorMitigation Methods.- Single Event Soft Error Mechanisms.- Modeling Single EventCrosstalk Noise in Nanometer Technologies.- Modeling of Single Event CouplingDelay and Speedup Effects.- Single Event Upset Hardening of Interconnects.- Soft-ErrorAware Power Optimization.- Dynamic Threshold Technique for Soft Error and SoftDelay Mitigation.

Arvustused

Book gives wide perspectives on the technical insights of fundamentals of sources and mitigation strategies of soft error rates in semiconductor memory devices . a valuable addition to a scientific library, as well as served as good introduction for memory reliability engineers or specialists and   industrials involved in the field of memory device reliability. This book is highly recommended for people who desire a better understanding of the theory and practice of SER and technical considerations in SER mitigations. (Chong Leong Gan, Microelectronics Reliability, Vol. 74 (81), 2017)

1 Introduction
1(10)
1.1 Terrestrial Radiation Sources, Single Event Transients and Soft Error Generation
1(3)
1.2 Circuit Level Modeling of a Radiation Particle Strike
4(3)
1.3 Soft Error Rate
7(4)
1.3.1 Error Rate Calculation Using Simulation Method
7(2)
References
9(2)
2 Mitigation of Single Event Effects
11(8)
2.1 Hardening Techniques
11(1)
2.2 System Level Techniques
11(1)
2.3 Device Level Techniques
12(1)
2.4 Circuit Level Hardening Techniques
13(4)
2.5 Summary
17(2)
References
17(2)
3 Transmission Gate (TG) Based Soft Error Mitigation Methods
19(12)
3.1 Basic TG Filtering Technique and Tunable Transient Filter
19(1)
3.2 TG with Varied Gate Bias for Soft Error Mitigation
20(4)
3.3 Effect of Body-Biasing on TG Mitigation Ability
24(1)
3.4 Temporal Sampling Application
25(1)
3.5 TG Mitigation Method Combined with Driver Sizing
26(5)
References
29(2)
4 Single Event Soft Error Mechanisms
31(18)
4.1 Introduction
31(1)
4.2 Soft Delay Error
32(1)
4.3 Radiation Induced Clock Jitter and Clock Pulse
33(1)
4.4 Single Event Crosstalk Noise
34(8)
4.4.1 Introduction
34(3)
4.4.2 Analysis Single Event Crosstalk
37(3)
4.4.3 Comparison Between SECN and SET Effects
40(2)
4.5 Single Event Crosstalk Delay Effects
42(7)
4.5.1 Analysis Single Event Coupling Delay
42(3)
4.5.2 Comparison Between SE Crosstalk Delay and Soft Delay
45(2)
References
47(2)
5 Modeling Single Event Crosstalk Noise in Nanometer Technologies
49(14)
5.1 Introduction
49(1)
5.2 The 4-π Template for Single Event Crosstalk Modeling
49(3)
5.3 Modeling of Passive Aggressors
52(2)
5.4 RC Trees and Branch Reduction
54(1)
5.5 Aggressor Waveform at the Coupling Node
55(2)
5.6 Noise Voltage Formulation
57(2)
5.7 Summary of the Model
59(1)
5.8 Validation of the Model
59(2)
5.9 Summary
61(2)
References
62(1)
6 Modeling of Single Event Coupling Delay and Speedup Effects
63(12)
6.1 Single Event Coupling Delay Prediction
63(5)
6.1.1 Calculating Maximum Value of Crosstalk Noise VM
64(2)
6.1.2 Summary of the Worst Case SECD Calculation Model
66(1)
6.1.3 Validation of the Worst Case SECD Calculation Model
67(1)
6.1.4 Section Summary
68(1)
6.2 Single Event Crosstalk Speedup
68(2)
6.3 Best-Case SE Crosstalk Delay Calculation
70(5)
6.3.1 Summary of the Proposed SECS Prediction
71(1)
6.3.2 Validation of the Proposed Model
72(2)
References
74(1)
7 Single Event Upset Hardening of Interconnects
75(10)
7.1 Introduction
75(1)
7.2 SE Crosstalk Mitigation Techniques
76(9)
7.2.1 Aggressor Driver Sizing
76(1)
7.2.2 Victim Driver Sizing
77(4)
7.2.3 Wire Sizing
81(1)
7.2.4 Wire Spacing
82(1)
7.2.5 Shielding Method
83(1)
References
83(2)
8 Soft-Error Aware Power Optimization
85(10)
8.1 Introduction
85(1)
8.2 Power Optimization and Reliability
86(1)
8.3 Analyzing the Effect of Threshold on SEU and Soft Delay Errors
87(2)
8.4 Body-Bias Techniques
89(6)
8.4.1 Reverse Body-Bias
89(1)
8.4.2 Forward Body-Bias
90(2)
References
92(3)
9 Dynamic Threshold Technique for Soft Error and Soft Delay Mitigation
95(10)
9.1 Various DTMOS Configurations
95(3)
9.2 Comparison of DTMOS Configurations
98(3)
9.3 Soft Error and Soft Delay Hardening Using DTMOS
101(2)
9.4 Summary
103(2)
References
103(2)
Index 105
Dr. Selahattin Sayil is an Associate Professor in the Philip M. Drayer Department of Electrical Engineering at Lamar University.  His research focuses on Radiation effects modeling and hardening at the circuit level, Reliability analysis of low power designs, and Interconnect modeling and noise prediction.