This text on VLSI circuits covers topics such as: sensors and displays; RF receivers; timing circuits; RF transmitters; low power SRAMs and DRAM DLLs; wireless building blocks; high speed communications; analog techniques; microprocessor circuits; and Nyquist convertors.
SESSION 1---Plenary Session I David Scott Welcome and Opening Remarks William Bidermann Takayasu Sakurai IMT-2000 Terminal and its Requirements for Device Technologies 2(4) K. Nagata Micromachined Micro Systems: Miniaturizaion Beyond Microelectronics 6(10) K. Najafi Ann Arbor SESSION 2---Sensors and Displays M. Horowitz M. Ikeda A Monolithic Surface Micromachined Z-Axis Gyroscope with Digital Output 16(4) X. Jiang J. Seeger M. Kraft* B. Boser 8-Bit/Color 1024x768 Microdisplay with Analog In-Pixel Pulse Width Modulation and Retinal Averaging Offset Correction 20(4) T. Blalock N. Gaddis K. Nishimura T. Knotts A Low Power, Low Noise, Ultra-Wide Dynamic Range CMOS Imager with Pixel-Parallel A/D Conversion 24(4) L. McIlrath A CMOS Image Sensor for Focal-Plane Low-Power Motion Vector Estimation 28(4) D. Handoko S. Kawahito Y. Tadokoro* M. Kumahara* A. Matsuzawa** SESSION 3---RF Receivers B. Razavi T. Miki A Wide-Band Direct Conversion Receiver with On-Chip A/D Converters 32(2) A. Parssinen J. Jussila J. Ryynanen L. Sumanen K. Kivekas K. Halonen A 5.2-GHz CMOS Receiver with 62-dB Image Rejection 34(4) B. Razavi A 2 GHz CMOS Double Conversion Downconverter with Robust Image Rejection Performance Against the Process and Temperature Variations 38(4) E. Song S.-I. Chae W. Kim A Single-Chip 2.4GHz Direct-Conversion CMOS Receiver for Wireless Local Loop Using One-Third Frequency Local Oscillator 42(6) K. Lee J. Park J.-W. Lee S.-W. Lee* H.-K. Huh* D.-K. Jeong* W. Kim* SESSION 4---Timing Circuits W. Lee D.-K. Jeong A CMOS 50 Duty Cycle Repeater Using Complementary Phase Blending 48(2) K. Nakamura M. Fukaishi Y. Hirota Y. Nakazawa M. Yotsuyanagi A Low Jitter Dual Loop DLL using Multiple VCDLs with a Duty Cycle Corrector 50(2) Y.-J. Jung S.-W. Lee D. Shim W. Kim C.-H. Kim* S.-I. Cho* On-Chip Picosecond Time Measurement 52(4) V. Gutnik A. Chandrakasan SESSION 5---RF Transmitters B. Razavi T. Miki A Common-Gate Switched, 0.9W Class-E Power Amplifier with 41 PAE in 0.25μ CMOS 56(2) C. Yoo Q. Huang A Translinear-Based Chip For Linear LINC Transmitters 58(4) B. Shi L. Sundstrom A SOI-BiCMOS RF-Transmitter for Personal Digital Cellular Communication (PDC) 62(4) S. Kishore G. Chang C. Hull A Si 2-GHz 5-bit LO-Phase-Shifting Downconverter for Adaptive Antennas 66(4) T. Yamaji H. Tanimoto S. Obayashi Y. Suzuki SESSION 6---Low Power SRAMs and DRAM DLLs W. K. Loh M. Matsui A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAMs 70(2) K. Agawa H. Hara T. Takayanagi T. Kuroda A 1.8V 18Mb DDR CMOS SRAM with Power Reduction Techniques 72(2) A. Kawasumi A. Suzuki H. Hatada Y. Takeyama O. Hirabayashi Y. Kameda T. Hamano* N. Otsuka A 256-Mb Double-Data-Rate SDRAM with a 10-mW Analog DLL Circuit 74(2) H. Yahata Y. Okuda H. Miyashita H. Chigasaki* B. Taruishi* T. Akiba* Y. Kawase* T. Tachibana* S. Ueda S. Aoyama A. Tsukimori K. Shibata* M. Horiguchi Y. Saiki Y. Nakagome A Skew and Jitter Suppressed DLL Architecture for High Frequency DDR SDRAMs 76(4) T. Hamamoto S. Kawasaki K. Furutani K. Yasuda Y. Konishi RUMP SESSIONS 80 Circuit and System Technology in the year 2010 J. Woo T. Shibata S. Borkar T. Kozawa How to Prosper in a World of Embedded DRAM P. Gillingham M. Motomura B. Prince Are Analog CMOS Technologies Near Extinction? B. Razavi T. Tsukahara Package Modeling: Or Silicon in System Debug? B. Gieseke Y. Ohtomo G. Taylor Y. Ohtomo SESSION 7---Plenary Session II David Scott Masakazu Yamashina Addressing ESD for Microprocessors and ASICs in 21st Century Technologies 84 A. Amerasekera Where Does Memory Go in the 21C? (Evolution and Revolution of Memory Technology) 88 C.-G. Hwang SESSION 8---Wireless Building Blocks I G. Nasserbakht M. Katakura A 2 dB NF, Fully Differential, Variable Gain, 900 MHz CMOS LNA 94 E. Sacchi I. Bietti F. Gatta* F. Svelto** R. Castello* Sub 1-V 5-GHz-Band Up- and Down-Conversion Mixer Cores in 0.35-μ CMOS 98 T. Wakimoto T. Hatano C. Yamaguchi H. Morimura S. Konaka A 25.9-GHz Voltage-Controlled Oscillator Fabricated in a CMOS Process 100 C.-M. Hung L. Shi* I. Lagnado** K.K. O Analysis and Design of Silicon Bipolar Distributed Oscillators 102 A. Hajimiri H. Wu SESSION 9---DRAMs P. Gillingham C. Kim A Next Generation Channeled-DRAM Architecture with Direct Background-Operation and Delayed Channel-Replacement Techniques 108 Y. Yabe N. Nakamura Y. Aimoto M. Motomura Y. Matsui Y. Asakura A 2.5V, 2.0Gbyte/s 288M Packet-Based DRAM with Enhanced Cell Efficiency and Noise Immunity 112 K.-H. Kyung H.-C. Lee K.-W. Song H.-S. Song K.-W. Jung D.-Y. Lee C. Kim S.-I. Cho A DDR/SDR-Compatible SDRAM Design with a Three-Size Flexible Column Redundancy 116 T. Sakata S. Morita* O. Nagashima H. Noda T. Takahashi* T. Sonoda* H. Tadokoro* H. Ichikawa T. Adou S. Hanzawa M. Ohi S. Ookuma Y. Suzuki* H. Tanaka* K. Ishii CMOS-Logic-Circuit-Compatible DRAM Circuit Designs for Wide-Voltage and Wide-Temperature-Range Applications 120 H. Mizuno N. Oodaira* Y. Kanno T. Sakata T. Watanabe SESSION 10---High Speed Communications I M. Horowitz H. Yamauchi Adaptive Bandwidth DLLs and PLLs Using Regulated Supply CMOS Buffers, S. Sidiropoulos 124 D. Liu* J. Kim* G. Wei* M. Horowitz* 1.6 Gb/s/pin 4-PAM Signaling and Circuits for a Multi-Drop Bus 128 J. Zerbe P. Chau C. Werner T. Thrush D. Perino B. Garlepp* K. Donnelly Sub-Picosecond Jitter SiGe BiCMOS Transmit and Receive PLLs for 12.5Gbaud Serial Data Communication 132 D. Friedman M. Meghelli B. Parker H. Ainspan M. Soyuer A 10-Gb/s CMOS Clock and Data Recovery Circuit 136 J. Savoj B. Razavi SESSION 11---Analog Techniques B. Razavi D.-K. Jeong A 50-mW 14-bit 2.5-MS/s Σ-Δ Modulator in a 0.25μ Digital CMOS Technology 142 P. Balmelli Q. Huang F. Piazza Linearization Method for Fast Voltage-to-Current Converters 144 C. Paulus* R. Thewes A Variable Gain CMOS Amplifier with Exponential Gain Control 146 C. Mangelsdorf A New Model for Thermal Channel Noise of Deep Submicron MOSFETs and its Application in RF-CMOS Design 150 G. Knoblinger P. Klein M. Tiebout SESSION 12---Flash Memories H. Pon M. Hiraki A Dual Page Programming Scheme for High-Speed Multi-Gb-Scale NAND Flash Memories 156 K. Takeuchi T. Tanaka 1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications 158 R. McPartland R. Singh* A 60ns Access 32kByte 3-Transistor Flash for Low Power Embedded Applications 162 T. Ikehashi J. Noda K. Imamiya M. Ichikawa A. Iwata T. Futatsuyama A Selective Verify Scheme for Achieving a 5-MB/s Program Rate in 3-bit/cell Flash Memories 166 H. Kurata N. Kobayashi K. Kimura S. Saeki* T. Kawahara SESSION 13---High Speed Communications II B. Razavi Y. Ohtomo A Si BiCMOS Trans-Impedance Amplifier for 10Gb SONET Receiver 170 H. H. Kim S. Chandrasekhar C. Burrus J. Bauman A 156 Mbps CMOS Laser Diode Driver for Optical Burst-Mode Transmission 174 T. Matsuyama M. Miki T. Inoue* N. Murakami N. Ueno** A Constant Slew-Rate Ethernet Line Driver 176 D. Nack Analog Front End IC for Category I & II ADSL 178 J. Guido V. Leung J. Kenney J. Trackim A. Agrillo E. Zimany R. Shariatdoust SESSION 14---Microprocessor Circuits B. Gieseke M. Motomura A Clock Distribution Network for Microprocessors 184 P. Restle T. McNamara* D. Webber* P. Camporese* K. Eng* K. Jenkins D. Allen** M. Rohn** M. Quaranta** D. Boerstler# C. Alpert# C. Carter# R. Bailey# J. Petrovic# B. Krauter# B. McCredie# Comparative Delay, Noise and Energy of High-Performance Domino Adders with Stack Node Preconditioning (SNP) 188 Y. Ye J. Tschanz S. Narendra S. Borkar M. Stan* V. De 470ps 64bit Parallel Binary Adder 192 J. Park H. Ngo* J. Silberman* S. Dhong* 1 GHz Leading Zero Anticipator Using Independent Sign-Bit Determination Logic 194 K. T. Lee K. Nowka SESSION 15---Digital Circuit Techniques J. Alvarez T. Kuroda A Low-Power Adiabatic Driver System for AMLCDs 198 R. Lal W. Athas* L. Svensson** Level Converters with High Immunity to Power-Supply Bouncing for High-Speed Sub-1-V LSIs 202 Y. Kanno H. Mizuno K. Tanaka T. Watanabe VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem 204 Y. Mitsuyama Z. T. Onoye* I. Shirakawa SESSION 16---Nyquist Converters and Filters L. McIlrath A 12b 105Msample/S, 850mW Analog to Digital Converter 208 C. Michalski An 8-bit 125Ms/s CMOS Folding ADC for Gigabit Ethernet LSI 212 K. Yoon J. Lee D.-K. Jeong W. Kim A 200MHz, 3mW, 16-Tap Mixed-Signal FIR Filter 214 M. Figueroa C. Diorio An Adaptive Analog Noise-Predictive Decision-Feedback Equalizer 216 M. Q. Le P. Hurst J. Keane SESSION 17---Cache Memory H. Pon T. Mori A 1.6 ns Access, 1 GHz Two-Way Set-Predicted and Sum-Indexed 64-kByte Data Cache 220 J. Silberman N. Aoki* N. Kojima* S. H. Dhong** T.J. Watson A 2 GHz Cycle, 430 ps Access Time 34 Kb L1 Directory SRAM in 1.5 V, 0.18μ CMOS Bulk Technology 222 R. Joshi S. Kowalczyk Y. Chan* W. Huott* S. Wilson* G. Scharff* The Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-0.18μ Technologies 226 K. Zhang K. Hose V. De B. Senyk A 16GB/s, 0.18μ Cache Tile for Integrated L2 Caches from 256KB to 2MB 228 J. Miller J. Conary D. DiMarco SESSION 18---Wireless Building Blocks II L. McIlrath M. Katakura A 2-V 1.8-GHz Fully-Integrated CMOS Dual-Loop Frequency Synthesizer 234 T. K. Kan H. Luong A 1.5-V 900-MHz Monolithic CMOS Fast-Switching Frequency Synthesizer for Wireless Applications 238 C.-W. Lo H.C. Luong A 1.8-GHz Self-Calibrated Phase-locked Loop with Precise I/Q Matching 242 C.-H. Park O. Kim* B. Kim A Very Low Power Channel Select Filter for IS-95 CDMA Receiver with On-Chip Tuning 244 T. Kuo B. Lusignan*
