These conference prodeedings cover such topics as: copper interconnects; novel devices; high-K dielectrics; process technology; embedded DRAM; gate electrode engineering; DRAM cells; gate oxide scaling and reliability; DRAM capacitors; and high performance RF.
SESSION 1--Plenary Session Craig Lage Tadashi Nishimura Welcome and Opening Remarks Antonio Alvarez Eiji Takeda VLSI Symposium and Silicon Technology: A Twenty Year Perspective 2(2) Youssef El-Mansy New Frontiers of Sub-100nm VLSI Technology - Moving Toward Device and Circuit Co-Design 4(6) Masao Fukuma SESSION 2--Highlights R. De Keersmaecker T. Kunio A 0.13μm DRAM Technology for Giga bit Density Stand-alone and Embedded DRAMs 10(2) K.N. Kim T.Y. Chung H.S. Jeong J.T. Moon Y.W. Park G.T. Jeong K.H. Lee G.H. Koh D.W. Shin Y.S. Hwang D.W. Kwak H.S. Uh D.W. Ha J.W. Lee S.H. Shin M.H. Lee Y.S. Chun J.K. Lee B.J. Park J.H. Oh J.G. Lee S.H. Lee A Modular 0.13μm Bulk CMOS Technology for High Performance and Low Power Applications 12(2) L. Han S. Biesemans J. Heidenreich K. Houlihan C. Lin V. McGahay T. Schiml A. Schmidt U. Schroeder M. Stetter C. Wann D. Warner R. Mahnkopf B. Chen A 70 nm Gate Length CMOS Technology with 1.0 V Operation 14(2) A. Ono K. Fukasaku T. Matsuda T. Fukai N. Ikezawa K. Imai T. Horiuchi High Quality La2O3 and Al2O3 Gate Dielectrics with Equivalent Oxide Thickness 5-10A 16(4) A. Chin Y.H. Wu S.B. Chen C.C. Liao W.J. Chen SESSION 3--Copper Interconnect R. Havemann J. Ida Highly Thermal-Stable, Plasma-Polymerized BCB Polymer Film (k=2.6) for Cu Dual-Damascene Interconnects 20(2) J. Kawahara K. Shiba M. Tagami M. Tada S. Saito T. Onodera K. Kinoshita M. Hiroi A. Furuya K. Kikuta Y. Hayashi A 0.20μ CMOS Technology with Copper-Filled Contact and Local Interconnect 22(2) R. Islam S. Venkatesan M. Woo R. Nagabushnam D. Denning K. Yu O. Adetutu J. Farkas T. Stephens T. Sparks Cooper Distribution Behavior Near a SiO2/Si Interface by Low-Temperature (<400°C) Annealing and its Influence on Electrical Characteristics of MOS-Capacitors <400°C) Annealing and its Influence on Electrical Characteristics of MOS-Capacitors 24(2) K. Hozawa T. Itoga S. Isomae J. Yugami M. Ohkura Copper Contamination Induced Degradation of MOSFET Characteristics and Reliability 26(4) M. Inohara H. Sakurai T. Yamaguchi H. Tomita T. Iijima H. Oyamatsu T. Nakayama H. Yoshimura Y. Toyoshima SESSION 4--Novel Devices Y. Taur E. Suzuki Miss Tunnel Diode: A Capacitorless 4F2 Memory Cell for Sub-0.1 μm Era 30(2) H. Matsuoka T. Sakata S. Kimura Mass-Productive High Performance 0.5μm Embedded FRAM Technology with Triple Layer Metal 32(2) A. Itoh Y. Hikosaka T. Saito H. Naganuma H. Miyazawa Y. Ozaki Y. Kato S. Mihara H. Iwamoto S. Mochizuki M. Nakamura T. Yamazaki A Novel 1T1C Capacitor Structure for High Density FRAM 34(2) N.W. Jang Y.J. Song H.H. Kim D.J. Jung B.J. Koo S.Y. Lee S.H. Joo K.M. Lee K. Kim SiGe Heterojunctions in Epitaxial Vertical Surrounding-Gate MOSFETs 36(4) C.K. Date J.D. Plummer SESSION 5--High-K Dielectrics J. Lee S. Kawamura Performance of MOSFETs with Ultra Thin ZrO2 and Zr Silicate Gate Dielectrics 40(2) W.-J. Qi R. Nieh B.H. Lee K. Onishi L. Kang Y. Jeon J. Lee V. Kaushik B.-Y. Neuyen L. Prabhu K. Eisenbeiser J. Finder Novel MIS Al2O3 Capacitor as a Prospective Technology for Gbit DRAMs 42(2) I.S. Park B.T. Lee S.J. Choi J.S. Im S.H. Lee K.Y. Park J.W. Lee Y.W. Hyung Y.K. Kim H.S. Park Y.W. Park S.I. Lee M.Y. Lee Single-Layer Thin HfO2 Gate Dielectric with n+ - Polysilicon Gate 44(2) L. Kang Y. Jeon K. Onishi B.H. Lee W-J. Qi R. Nieh S. Gopalan J.C. Lee Characteristics of AL203 Gate Dielectric Prepared by Atomic Layer Deposition for Giga Scale CMOS DRAM Devices 46(4) D.-G. Park H.-J. Cho C. Lim I.-S. Yeo J.-S. Roh C.-T. Kim J.-M. Hwang SESSION 6--Process Technology W. Arnold J.-M. Hwang A Novel CVD Polymeric Anti-Reflective Coating (PARC) for DRAM 50(2) K. Linliu M.-R. Kuo Y.-R. Huang S.-C. Lin S.-P. Jeng C.-S. Chen Making 50nm Transistors with 248 nm Lithography 52(2) P. Stolk P. Dirksen C. Juffermans R. Roes A. Montree J. v. Wingerden W. de Laat W. Gehoel-v. Ansem M. Kaiser J. Kwinten C. van der Poel EB Projection Lithography for 60-80nm ULSI Fabrication 54(2) K. Tokunaga F. Koba M. Miyasaka Y. Takaishi K. Noda H. Yamashita K. Nakajima H. Nozue A High Performance Drying Method Enabling Clustered Single Wafer Wet Cleaning 56(4) P. Mertens G. Doumen J. Lauerhaas K. Kenis W. Fyen M. Meuris S. Arnauts K. Devriendt R. Vos M. Heyns SESSION 7--Embedded DRAM R. Mahnkopf T. Eimori A Simple Embedded DRAM Process for 0.16-μm CMOS Technologies 60(2) C.T. Liu P.W. Diodato S. Rogers W.Y.C. Lai C.J. Chen E.J. Lloyd C.Y. Sun D. Barr R. Liu C.P. Chang L. Trimble C.S. Pai H. Vaidya High Density Embedded DRAM Technology with 0.38μm Pitch in DRAM and 0.42μm Pitch in LOGIC by W/PolySi Gate and Cu Dual Damascene Metallization 62(2) N. Takenaka M. Segawa T. Uehara S. Akamatsu M. Matsumoto K. Kurimoto T. Ueda H. Watanabe T. Matsutani K. Yoneda A. Koshio Y. Kato M. Insuishi T. Oashi K. Tsukamoto S. Komori K. Tomita T. Inbe A. Ohsaki T. Hanawa S. Sakamori M. Shirahata J. Tsuchimoto T. Eimori A 0.17μm Embedded DRAM Technology with 0.23μm2 Cell Size and Advanced CMOS Logic 64(2) H. Wurzer K. Feldner W. Graf G. Curello J. Faul D. Weber A. Kieslich 0.25 μm Merged Bulk DRAM and SOI Logic Using Patterned SOI 66(4) R. Hannon S.S.K. Iyer D. Sadana J. Rice H. Ho B. Khan S.S. Iyer SESSION 8--Gate Electrode Engineering C. Osburn K. Shibahara Damascene Metal Gate MOSFETs with Co Silicided Source/Drain and High-k Gate Dielectrics 70(2) K. Matsuo T. Saito A. Yagishita T. Iinuma A. Murakoshi K. Nakajima S. Omoto K. Suguro Dual-Metal Gate Technology for Deep-Submicron CMOS Transistors 72(2) Q. Lu Y.C. Yeo P. Ranade H. Takeuchi T-J King C. Hu S.C. Song H.F. Luan D-L Kwong A Thin Amorphous Silicon Buffer Process for Suppression of W Polymetal Gate Depletion in PMOS 74(2) F. Ohtake Y. Akasaka A. Murakoshi K. Suguro T. Nakanishi Deep Sub-100nm CMOS with Ultra Low Gate Sheet Resistance by NiSi 76(4) Q. Xiang C. Woo E. Paton J. Foster B. Yu M.-R. Lin SESSION 9--DRAM Cells C. Dennison H. Kuroda A 0.135 μm2 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM 80(2) C. Radens U. Gruening J. Mandelman M. Seitz T. Dyer D. Lea D. Casarotto L. Clevenger L. Nesbit R. Malik S. Halle S. Kudelka H. Tews R. Divakaruni J. Sim A. Strong D. Tibbel N. Arnold S. Bukofsky J. Preuninger G. Kunkel G. Bronner Transistor on Capacitor (TOC) Cell with Quarter Pitch Layout for 0.13μm DRAMs and Beyond 82(2) M. Sato S. Ishibashi T. Kajiyama M. Sakuma I. Mizushima Y. Tsunashima F. Shoji H. Yano A. Nitayama T. Hamamoto Scaling Guideline of DRAM Memory Cells for Maintaining the Retention Time 84(2) S. Ueno Y. Inoue M. Inuishi Improvement of the Tail Component in Retention Time Distribution Using Buffered N-Implantation With Tilt and Rotation (BNITR) for 0.2 (m DRAM Cell and Beyond 86(4) I. Kim N. Kim H. Jung H. Kwon S. Ok J. Kim P. Sim J. Park D. Park S. Jang SESSION 10--Gate Oxide Scaling and Reliability C.S. Pai M. Ohkura Limits of Gate-Oxide Scaling in Nano-Transistors 90(2) B. Yu H. Wang C. Riccobene Q. Xiang M.R. Lin NBTI Enhancement by Nitrogen Incorporation Into Ultrathin Gate Oxide for 0.10-μm Gate CMOS Generation 92(2) N. Kimizuka K. Yamaguchi K. Imai T. Iisuka C.T. Liu R.C. Keller T. Horiuchi Breakdown Measurements of Ultra-Thin SiO2 at Low Voltage 94(2) J. Stathis A. Vayshenker P. Varekamp E. Wu C. Montrose J. McKenna D. DiMaria L.-K. Han E. Cartier R. Wachnik B. Linder Quantitative Yield and Reliability Projection from Antenna Test Results - A Case Study 96(6) P. Mason K.P. Cheung D.K. Hwang M. Creusen R. Degraeve B. Kaczer SESSION 11--DRAM Capacitors T. Seidel S.-I. Lee Development of CVD-Ru/Ta2O5/CVD-TiN Capacitor for Multigigabit-Scale DRAM Generation W.D. Kim J.W. Kim S.J. Won S.D. Nam B.Y. Nam C.Y. Yoo Y.W. Park S.I. Lee M.Y. Lee A Conformal Ruthenium Electrode for MIM Capacitors in Gbit DRAMs Using the CVD Technology Based on Oxygen-Controlled Surface Reaction 102(2) M. Hiratani T. Nabatame Y. Matsui Y. Shimamoto Y. Sasago Y. Nakamura Y. Ohji I. Asano S. Kimura Low Temperature (<500(C) SrTiO3 Capacitor Process Technology for Embedded DRAM <500(C) SrTiO3 Capacitor Process Technology for Embedded DRAM 104(2) J. Nakahira M. Kiyotoshi S. Yamazaki M. Nakabayashi S. Niwa K. Tsunoda J. Lin A. Shimada M. Izuha T. Aoyama H. Tomita K. Eguchi K. Hieda A New Cell Technology for the Scalable BST Capacitor Using Damascene-formed Pedestal Electrode with a (Pt-Ir) Alloy Coating 106(4) H. Itoh Y. Tsunemine A. Yutani T. Okudaira K. Kashihara M. Inuishi M. Yamamuka T. Kawahara T. Horikawa T. Ohmori S. Satoh SESSION 12--Gate and S/D Engineering G. De Santi S. Ohnishi Reliable and Enhanced Performances of Sub-0.1 μm pMOSFETs Doped by Low Biased Plasma Doping 110(2) D. Lenoble F. Arnaud A. Grouillet R. Liebert S. Walther S. Felch Z. Fang M. Haond Ultra Low Energy Arsenic Implant Limits on Sheet Resistance and Junction Depth 112(2) R. Kasnavi P. Griffin J. Plummer High Performance pMOSFETs with Ni(SixGe1-x)/Poly-Si0.8Ge0.2 Gate 114(2) J.-H. Ku C.-J. Choi S. Song S. Choi K. Fujihara H.-K. Kang S.-I. Lee H.-G. Choi D.-H. Ko Low-Leakage and Highly-Reliable 1.5 nm SiON Gate-Dielectric Using Radical Oxynitridation for Sub-0.1 μm CMOS 116(4) M. Togo K. Watanabe T. Yamamoto N. Ikarashi K. Shiba T. Tatsumi H. Ono T. Mogami SESSION 13--Advanced Non-Volatile Memory M.-R. Lin S.S. Chung 0.18μm Modular Triple Self-Aligned Embedded Split-Gate Flash Memory 120(2) R. Mih J. Harrington K. Houlihan H. K. Lee K. Chan J. Johnson B. Chen J. Yan∧ A. Schmidt∧ C. Gruensfelder∧ K. Kim∧ D. Shum∧ C. Lo# D. Lee# A. Levi# C. Lam Twin MONOS Cell with Dual Control Gates 122(2) Y. Hayashi S. Ogura T. Saito T. Ogura A Flash EEPROM Cell with Self-Aligned Trench Transistor & Isolation Structure 124(2) K. Nakagawa K. Yoshida S. Masuda A. Yoshino I. Sakai Split Gate Cell with Phonon Assisted Ballistic CHE Injection 126(4) T. Saito S. Ogura T. Ogura T. Yuda Y. Kawazu M. Ikegami A. Uchiyama T. Ono SESSION 14--Channel Engineering R. Rakkhit Y.-J. Mii Multiple SiGe Well: A New Channel Architecture for Improving Both NMOS and PMOS Performances 130(2) J. Alieu T. Skotnicki E. Josse J.-L. Regolini G. Bremond Auger Recombination Enhanced Hot Carrier Degradation in nMOSFETs with Positive Substrate Bias 132(2) L.P. Chiang C.W. Tsai T. Wang U.C. Liu M.C. Wang L.C. Hsia Impact of Ion Implantation Statistics on VT Fluctuations in MOSFETs: Comparison Between Decaborane and Boron Channel Implants 134(2) H. Tuinhout F. Widdershoven P. Stolk J. Schmitz B. Dirks K. van der Tak P. Bancken J. Politiek Direct Measurement of Vth Fluctuation Caused by Impurity Positioning 136(8) T. Tanaka T. Usuki Y. Momiyama T. Sugii RUMP SESSIONS S. Borkar T. Kozawa Circuit and System Technology in the year 2010 J. Woo T. Shibata S. Borkar T. Kozawa DRAM Scaling Challenges and Innovations Between Now and 2010: How Far Can the DRAM Cell Shrink? C. Dennison F. Horiguchi Lithography For Sub-100nm, Optical vs. Non-Optical Christopher Spence Shinji Okazaki Novel Structures and Processes for Continued MOSFET Scaling: What, When, and Whether? Don Monroe Bell Labs SESSION 15--Technologies for System-on-a-Chip L. Su T. Nakamura A CMOS Technology Platform for 0.13(m Generation SOC (System on a Chip) 144(2) H. Yoshimura T. Nakayama M. Nishigohri M. Inohara K. Miyashita E. Morifuji A. Oishi H. Kawashima M. Habu H. Koike H. Takato Y. Toyoshima H. Ishiuchi A 0.15 (m CMOS Foundry Technology with 0.1 (m Devices for High Performance Applications 146(2) C. Diaz M. Chang W. Chen M. Chiang H. Su S. Chang P. Lu C. Hu K. Pan C. Yang L. Chen C. Su C. Wu Ch. Wang C.C. Wang J. Shih H. Hsieh H. Tao S. Jang M. Yu S. Shue B. Chen T. Chang C. Hou B.K. Liew K.H. Lee Y.C. Sun A Triple Gate Oxide CMOS Technology Using Fluorine Implant for System-On-A-Chip 148(2) Y. Goto K. Imai E. Hasegawa T. Ohashi N. Kimizuka T. Toda N. Hamanaka T. Horiuchi A 180nm Copper/Low-k CMOS Technology with Dual Gate Oxide Optimized for Low Power and Low Cost Consumer Wireless Applications 150(4) G.C.-F. Yeap F. Nkansah J. Chen S. Jallepalli D. Pham T. Lii A. Nangia P. Le D. Hall D. Menke J. Sun A. Das P. Gilbert F. Huang J. Sturtevant K. Green J. Lu J. Benavidas E. Banks J. Chung C. Lage SESSION 16--High Performance RF/Analog C. Van Der Poel T. Shibata Impact of 0.18 μm SOI CMOS Technology Using Hybrid Trench Isolation with High Resistivity Substrate on Embedded RF/Analog Applications 154(2) S. Maeda Y. Wada K. Yamamoto H. Komurasaki T. Matsumoto Y. Hirano T. Iwamatsu Y. Yamaguchi T. Ipposhi K. Ueda K. Mashiko S. Maegawa M. Inuishi Well-Controlled, Selectively Under-Etched Si/SiGe Gates for RF and High Performance CMOS 156(2) T. Skotnicki M. Jurczak J. Martins M. Paoli B. Tormen R. Pantel C. Hernandez I. Campidelli E. Josse G. Ricci J. Galvier CMOS with Active Well Bias for Low-Power and RF/Analog Applications 158(2) C. Wann J. Harrington R. Mih S. Biesemans K. Han R. Dennard O. Prigge C. Lin R. Mahnkopf B. Chen An Epitaxial Channel MOSFET for Improving Flicker Noise Under Low Supply Voltage 160(4) T. Ohguro R. Hasumi T. Ishikawa M. Nishigori H. Oyamatsu F. Matsuoka SESSION 17--Advanced SRAM Technology J. Watt F. Matsuoka A 0.99-μm2 Loadless Four-Transistor SRAM Cell in 0.13-μm Generation CMOS Technology 164(2) S. Masuoka K. Noda S. Ito K. Matsui K. Imai N. Yasuzato H. Kawamoto N. Ikezawa K. Ando S. Koyama T. Tamura Y. Yamada T. Horiuchi A Highly Versatile 0.18μm CMOS Technology with Dense Embedded SRAM 166(2) M. Bhat S. Shi P. Grudowski C. Feng B. Lee R. Nagabushnam J. Moench C. Gunderson P. Schani L. Day S. Bishop H. Tian J. Chung C. Lage J. Ellis N. Herr P. Gilbert A. Das F. Nkansah M. Woo M. Wilson D. Derr L. Terpolilli K. Weidemann R. Stout A. Hamilton T. Lii F. Huang K. Cox J. Scott A Novel Logic Compatible Gain Cell with Two Transistors and One Capacitor 168(2) N. Ikeda T. Terano H. Moriya T. Emori T. Kobayashi A Partially Depleted 1.8V SOI CMOS SRAM Technology Featuring a 3.77μm2 Cell 170(4) K. Cox J. Scott S. Bishop M. Bhat B. Nettleton D. Pan M. Hamilton D. Chang L. Day P. Schani SESSION 18--Device Technology S. Thompson H. Hanafusa Scaling Challenges and Device Design Requirements for High Performance Sub-50nm Gate Length Planar CMOS Transistors 174(2) T. Ghani K. Mistry P. Packan S. Thompson M. Stettler S. Tyagi M. Bohr Advantage of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide 176(2) Y. Saito K. Sekine N. Ueda M. Hirayama S. Sugawa T. Ohmi Advanced Shallow Trench Isolation to Suppress the Inverse Narrow Channel Effects for 0.24μm Pitch Isolation and Beyond 178(2) K. Horita T. Kuroi Y. Itoh K. Shiozawa K. Eikyu K. Goto Y Inoue M. Inuishi Silicide and Shallow Trench Isolation Line Width Dependent Stress Induced Junction Leakage 180(4) A. Steegen A. Lauwers M. de Potter G. Badenes R. Rooyackers K. Maex SESSION 19--High Performance CMOS G. Bomchil T. Tsuchiya A High Performance 0.13(m SOI CMOS Technology with Cu Interconnects and Low-k BEOL Dielectric 184(2) P. Smeys V. McGahay I. Yang J. Adkisson K. Beyer O. Bula Z. Chen B. Chu J. Culp S. Das A. Eckert L. Hadel M. Hargrove J. Herman L. Lin R. Mann E. Maciejewski S. Narasimha P. ONeil S. Rauch D. Ryan J. Toomey L. Tsou P. Varekamp R. Wachnik T. Wagner S. Wu C. Yu P. Agnello J. Connolly S. Crowder C. Davis R. Ferguson A. Sekiguchi L. Su R. Goldblatt T.C. Chen High-Performance 80-nm Gate Length SOI-CMOS Technology with Copper and Very-Low-k Interconnects 186(4) K. Sukegawa M. Yamaji K. Yoshie K. Furumochi T. Maruyama H. Morioka N. Naori T. Kubo H. Kanata M. Kai S. Satoh T. Izawa K. Kubota Sub-0.1μm CMOS with Source/Drain Extension Spacer Formed Using Nitrogen Implantation Prior to Thick Gate Re-Oxidation J. C. Hu A. Chatterjee M. Mehrotra J. Xu W.T. Shiau M. Rodder Design of Sub-100nm CMOSFETs: Gate Dielectrics and Channel Engineering 190(4) S. Song W. S. Kim J.S. Lee T.H. Choe J.H. Choi M.S. Kang U.I. Chung N. I. Lee K. Fujihara H.K. Kang S.I. Lee M.Y. Lee SESSION 20--Modeling R. Nowak S. Odanaka An Integrated Architecture for Global Interconnects in a Gigascale System-on-a-Chip (GSoC) 194(2) P. Zarkesh-Ha J. Meindl An Accurate Non-Quasistatic MOSFET Model for Simulation of RF and High Speed Circuits 196(2) X. Jin K. Cao J-J Ou W. Liu Y. Cheng M. Matloubian C. Hu Modeling Gate and Substrate Currents due to Conduction- and Valence-Band Electron and Hole Tunneling 198(2) W-C Lee C. Hu Vdd Impact on Propagation Pulse Width Variation in PD SOI Circuits 200(4) B. Min G. Workman D. Chang O. Zia Y. Yu R. Widenhofer B. Simon N. Cave H. Sanchez S. Veeraraghavan M. Mendicino B. Yeargain SESSION 21--Advanced SOI Devices and Modeling M. Cao Y. Omura Scalability Revisited: 100nm PD-SOI Transistors and Implications for 50nm Devices 204(2) K. Mistry T. Ghani M. Armstrong S. Tyagi P. Packan S. Thompson S. Yu M. Bohr A Partially-Depleted SOI Compact Model--Formulation and Parameter Extraction 206(2) S. K. H. Fung L. Wagner M. Sherony N. Zamdmer J. Sleight M. Michel E. Leobandung S. H. Lo T.C. Chen F. Assaderaghi A Compact FD-SOI MOSFETs Fabrication Process Featuring SixGe 1-x Gate and Damascene-Dummy SAC 208(2) D. Hisamoto T. Kachi S. Tsujikawa A. Miyauchi K. Kusukawa N. Sakuma Y. Homma N. Yokoyama F. Ootsuka T. Onai Advanced SOI-MOSFETs with Strained-Si Channel for High Speed CMOS - Electron/Hole Mobility Enhancement 210(4) T. Mizuno N. Sugiyama H. Satake S. Takagi SESSION 22--Deep Sub-Micron Reliability J. Woo S. S. Chung Gate Oxide Breakdown Under Current Limited Constant Voltage Stress 214(2) B. Linder J. Stathis R. Wachnik E. Wu S. Cohen A. Ray A. Vayshenker Impacts of Strained SiO2 on TDDB Lifetime Projection, Y. Harada 216(2) K. Eriguchi M. Niwa T. Watanabe I. Ohdomari TBD Prediction from Measurements at Low Field and Room Temperature using a New Estimator 218(2) A. Ghetti J. Bude G. Weber Practical Benefits of the Electromigration Short-Length Effect, Including a New Design Rule Methodology and an Electromigration Resistant Power Grid with Enhanced Wireability 220 R. Wachnik R. Filippi T. Shaw P. Lin
