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Testing of Interposer-Based 2.5D Integrated Circuits 1st ed. 2017 [Kõva köide]

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  • Formaat: Hardback, 182 pages, kõrgus x laius: 235x155 mm, kaal: 4203 g, 102 Illustrations, color; 16 Illustrations, black and white; XIV, 182 p. 118 illus., 102 illus. in color., 1 Hardback
  • Ilmumisaeg: 29-Mar-2017
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319547135
  • ISBN-13: 9783319547138
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Testing of Interposer-Based 2.5D Integrated Circuits 1st ed. 2017Suurem pilt
  • Formaat: Hardback, 182 pages, kõrgus x laius: 235x155 mm, kaal: 4203 g, 102 Illustrations, color; 16 Illustrations, black and white; XIV, 182 p. 118 illus., 102 illus. in color., 1 Hardback
  • Ilmumisaeg: 29-Mar-2017
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319547135
  • ISBN-13: 9783319547138
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783319547138.html
Märksõnad:

This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits.  The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies.  This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable.

1 Introduction
1(16)
1.1 The Evolution of 2.5D ICs
1(3)
1.1.1 3D ICs: A Paradigm Shift from Traditional Integrated Circuits
1(1)
1.1.2 2.5D ICs: An Alternative to 3D ICs
2(2)
1.2 Research Challenges and Motivation
4(3)
1.2.1 Pre-bond Interposer Testing
4(1)
1.2.2 Lack of Test Access
5(1)
1.2.3 Limited Ability for At-Speed Testing
5(1)
1.2.4 High-Density I/O Ports and Interconnects
6(1)
1.2.5 Reduced Number of Test Pins
6(1)
1.2.6 High Power Consumption
6(1)
1.3 Emerging Solutions for the Testing of 2.5D ICs
7(5)
1.4 Outline of the Book
12(5)
References
14(3)
2 Pre-bond Testing of the Silicon Interposer
17(32)
2.1 Background
18(1)
2.2 Proposed Test Architecture and Procedures
19(9)
2.2.1 Definition of Die Footprint
19(1)
2.2.2 Test Architecture
20(3)
2.2.3 Assembly and Test Flow
23(1)
2.2.4 Test Procedures
24(3)
2.2.5 Weighted Critical Area
27(1)
2.3 Test-Path Design
28(9)
2.3.1 Optimization Problem
28(4)
2.3.2 Proposed Algorithm
32(5)
2.4 Experimental Results
37(10)
2.4.1 Testing the Horizontal Interconnects
37(2)
2.4.2 Testing for Vertical Interconnects
39(2)
2.4.3 Evaluation of the Test-Path Design Method
41(6)
2.5 Conclusion
47(2)
References
47(2)
3 Post-bond Scan-Based Testing of Interposer Interconnects
49(32)
3.1 Problem Statement
50(1)
3.2 Proposed Test Architecture
51(2)
3.3 Test Application
53(7)
3.3.1 Open/Short-Defect Testing
54(1)
3.3.2 Delay-Defect Testing
54(4)
3.3.3 Test Structures for Bi-directional I/Os
58(2)
3.4 Integration with IEEE 1149.1
60(6)
3.5 Simulation Results
66(13)
3.5.1 Detection Capability for Open Defects
66(3)
3.5.2 Detection Capability for Short Defects
69(1)
3.5.3 Detection Capability for Delay Defects
70(5)
3.5.4 Architecture Simulation
75(3)
3.5.5 Area Overhead
78(1)
3.6 Conclusion
79(2)
References
79(2)
4 Test Architecture and Test-Path Scheduling
81(28)
4.1 Proposed Test Architecture
82(7)
4.1.1 Boundary-Scan Structure
82(1)
4.1.2 Modified TAP Controller
83(2)
4.1.3 Boundary-Scan Cells and Circuit Block
85(3)
4.1.4 Test Procedures
88(1)
4.2 Test-Path Design and Scheduling
89(9)
4.2.1 Structure of Additional Test Paths
91(1)
4.2.2 Minimization of Total Interconnect Test Cost
92(2)
4.2.3 Optimization in Alternative Scenarios
94(1)
4.2.4 Placement of Dies on the Test Path
95(3)
4.3 Simulation Results
98(9)
4.3.1 Test Architecture Simulation Results
98(2)
4.3.2 Case Study
100(1)
4.3.3 Area Overhead
101(1)
4.3.4 Test-Path Design and Scheduling Results
102(5)
4.4 Conclusion
107(2)
References
107(2)
5 Built-In Self-Test
109(26)
5.1 Related Prior Work
110(1)
5.2 Proposed BIST Architecture
110(3)
5.3 BIST Components
113(8)
5.3.1 Self-configuration of the In-BSC
113(1)
5.3.2 Pattern Generator
114(3)
5.3.3 Response Compactor
117(2)
5.3.4 BIST Controller
119(2)
5.4 Test Scheduling and Optimization
121(4)
5.5 Simulation Results
125(7)
5.5.1 BIST Architecture Simulation
125(1)
5.5.2 Case Study
126(2)
5.5.3 Overhead Analysis
128(1)
5.5.4 Test Scheduling Results
129(3)
5.6 Conclusion
132(3)
References
132(3)
6 ExTest Scheduling and Optimization
135(28)
6.1 Problem Statement
136(1)
6.2 Test Architecture and Current Solution
137(3)
6.3 Proposed Scheduling Strategies
140(6)
6.3.1 Scheduling Strategy for SoC Dies with Dedicated Wrappers
140(2)
6.3.2 Scheduling Strategy for Extremely Large SoC Dies
142(4)
6.4 Schedule Optimization
146(3)
6.4.1 Sharing of Inputs
146(2)
6.4.2 Output Removal
148(1)
6.5 Subgroup Configuration
149(4)
6.5.1 Independent Subgroup Configuration
150(1)
6.5.2 Dependent Subgroup Configuration
151(2)
6.6 Experimental Results
153(7)
6.6.1 Compression Ratio Analysis
154(2)
6.6.2 Scheduling Results
156(2)
6.6.3 Optimization Results
158(2)
6.6.4 Run-Time Analysis
160(1)
6.7 Conclusion
160(3)
References
161(2)
7 A Programmable Method for Low-Power Scan Shift in SoC Dies
163(16)
7.1 Problem Statement
164(1)
7.2 Related Prior Work and Shift-Clock Staggering
164(3)
7.2.1 Low-Power Testing
165(1)
7.2.2 Principle of Shift-Clock Staggering
165(2)
7.3 Optimization Problem and Exact Solution
167(2)
7.4 Proposed Heuristic Algorithm
169(2)
7.5 Experimental Results
171(6)
7.5.1 Assignment Results
171(3)
7.5.2 Evaluation of Shift-Clock Staggering Using Silicon Data
174(3)
7.6 Conclusion
177(2)
References
178(1)
8 Conclusions
179
8.1 Book Summary
179(1)
8.2 Future Directions
180
References
182
Ran Wang is a Senior DFT Engineer at NVIDIA in Santa Clara, CA. Dr. Wang received the B. Sci. degree from Zhejiang University, Hangzhou, China, in 2012, and the M.S.E and Ph.D degree from the Department of Electrical and Computer Engineering, Duke University in 2014 and 2016. His current research interests include testing and design-for-testability of 2.5D ICs and 3D ICs.

Krishnendu Chakrabarty is the William H. Younger Distinguished Professor of Engineering in the Department of Electrical and Computer Engineering at Duke University in Durham, NC.  He has been at Duke University since 1998. His current research is focused on: testing and design-for-testability of integrated circuits (especially 3D and multicore chips); digital microfluidics, biochips, and cyberphysical systems; optimization of digital print and production system infrastructure. His research projects in the recent past have also included chip cooling using digital microfluidics, wireless sensor networks, and real-time embedded systems. 



Prof. Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, India in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor in 1992 and 1995, respectively. He is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society.





Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper award, and 12 best paper awards at major conferences.  He is also a recipient of the IEEE Computer Society Technical Achievement Award and the Distinguished Alumnus Award from the Indian Institute of Technology, Kharagpur. He is a Research Ambassador of the University of Bremen (Germany) and a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany. He has held Visiting Professor positions at University of Tokyo and the Nara Institute of Science and Technology (as an Invitational Fellow of the Japan Society for the Promotion of Science) in Japan, and Visiting Chair Professor positions at Tsinghua University (Beijing, China) and National Cheng Kung University (Tainan, Taiwan).